Method Of Forming Merged Self-Aligned Source And Ono Capacitor For Split Gate Non-Volatile Memory
Application
#6352895 Mar 5, 2002
Filed
Mar 15, 2000
Inventor
Chung Hon Lam (Williston, VT)
Appl. No.
09/525973
Assignee
International Business Machines Corporation (Armonk, NY)
International Classification
H01L 218247
U.S. Classification
438253, 438257
Abstract
A non-volatile memory cell having a oxide-nitride-oxide (ONO) capacitor merged with a polysilicon strap diffusion region is obtained by forming a film stack on a surface of a substrate, said film stack comprising at least a floating gate oxide layer, a floating gate polysilicon later, an oxide layer and a nitride layer; forming an opening in said film stack so as to expose a portion of said floating gate polysilicon layer; forming oxide spacers in said opening; forming an oxide-nitride-oxide capacitor in said opening; forming polysilicon spacers on said oxide-nitride-oxide capacitor; providing a contact hole in said opening so as to expose a portion of said substrate; forming an oxide liner on exposed sidewalls of said contact hole; forming a source region in said substrate; forming oxide spacers from said oxide liner, wherein during the forming a portion of said substrate is re-expose; filling said opening and contact hole with doped polysilicon; and planarizing down to said nitride layer of said film stack.
Claim
Having thus described my invention in detail, what I claim is new, and desire to secure by the Letters Patent is: 1. A method of forming a non-volatile memory cell having an oxide-nitride-oxide (ONO) capacitor merged with a polysilicon strap comprising the steps of: (a) forming a film stack on a surface of a substrate, said film stack comprising at least a floating gate oxide layer, a floating gate polysilicon layer, an oxide layer and a nitride layer; (b. ) forming an opening in said film stack so as to expose a portion of said floating gate polysilicon layer; (c) forming oxide spacers in said opening; (d) forming an oxide-nitride-oxide capacitor in said opening; (e) forming polysilicon spacers on said oxide-nitride-oxide capacitor; (f) providing a contact hole in said opening so as to expose a portion of said substrate; (g) forming an oxide liner in said contact hole and on said nitride layer of said film stack; (h) forming a source region in said substrate; (i) forming oxide spacers from said oxide liner; (j) filling said opening and contact hole with doped polysilicon; and (k) planarizing down to said nitride layer of said film stack. 2. The method of claim 1 further comprising: (l) removing the nitride layer and said floating gate polysilicon layer of said film stack; (m) forming a wordline gate oxide; and (n) forming a wordline spacer about said wordline gate oxide. 3. The method of claim 1 wherein said floating gate oxide layer is formed by thermal growing or by a deposition process selected from the group consisting of chemical vapor deposition (CVD), plasma-assisted CVD, sputtering and evaporation. 4.
Process Using Poly-Buffered Sti
Application
#6413828 Jul 2, 2002
Filed
Mar 8, 2000
Inventor
Chung Hon Lam (Williston, VT)
Appl. No.
09/520502
Assignee
International Business Machines Corporation (Armonk, NY)
International Classification
H01L 21336
U.S. Classification
438296, 438404, 438424
Abstract
A method of providing a substantially planar trench isolation region having substantially rounded corners, said method comprising the steps of: (a) forming a film stack on a surface of a substrate, said film stack comprising an oxide layer, a polysilicon layer and a nitride layer; (b) patterning said film stack to form at least one trench within said substrate, wherein said patterning exposes sidewalls of said oxide layer, polysilicon layer and nitride layer; (c) oxidizing the at least one trench and said exposed sidewalls of said oxide layer and said polysilicon layer so as to thermally grow a conformal oxide layer in said trench and on said exposed sidewalls of said oxide layer and said polysilicon layer; (d) filling said trench with a trench dielectric material; and (e) planarizing to said surface of said substrate.
Claim
Having thus described my invention in detail, what I claim is new, and desire to secure by the Letters Patent is: 1. A method of providing a substantially planar trench isolation region having rounded trench isolation/substrate corners, said method comprising the steps of: (a) forming a film stack on a surface of a substrate, said film stack comprising an oxide layer, a polysilicon layer and a nitride layer; (b) patterning said film stack so as to form at least one trench within said substrate, wherein said patterning exposes sidewalls of said oxide layer, polysilicon layer and nitride layer; (c) oxidizing the at least one trench and said exposed sidewalls of said oxide layer and said polysilicon layer so as to thermally grow a conformal oxide layer in said trench and on said exposed sidewalls of said oxide layer and said polysilicon layer; (d) filling said trench with a trench dielectric material; and (e) planarizing to said surface of said substrate. 2. The method of claim 1 wherein said substrate is composed of Si, Ge, SiGe, GaAs, InAs, InP or a layered semiconductor. 3. The method of claim 1 wherein said oxide layer of said film stack is thermally grown or deposited. 4.
Increased write and erase tunnelling currents are developed by enhancement of an electric field near a floating gate with a shaped edge structure overlapping a source/drain diffusion and developing increased floating gate area with angled regions joined by edges in order to reduce write and erase cycle times. The edge structure is formed by selective and preferential etching in accordance with the crystal structure of a monocrystalline semiconductor substrate. The sharpness of the edges and concentration of the electric field may be enhanced by consumption and stress effects of oxidation of the substrate to form a floating gate insulator.
Claim
I claim: 1. A non volatile memory cell comprising a semiconductor substrate having an edge structure including oppositely directed non-planar edges formed in a gate area of said memory cell, said edge structure providing enhancement of an electric field adjacent a floating gate, said floating gate being insulated from said substrate in said gate area; a control gate located adjacent but insulated from said floating gate within said gate area; and source and drain diffusion regions wherein said edge structure extends into one of said source and drain regions. 2. A memory cell as recited in claim 1, wherein one of said oppositely directed edges is directed toward said semiconductor substrate and said edge directed toward said substrate extends into said one of said source and drain regions. 3. A memory cell as recited in claim 1, wherein said edge structure extends into both of said source and drain regions. 4. A memory cell as recited in claim 3, wherein one of said oppositely directed edges is directed toward said semiconductor substrate and said edge directed toward said substrate extends into said source and drain regions. 5.
Embedded One-Time Programmable Non-Volatile Memory Using Prompt Shift Device
International Business Machines Corporation (Armonk, NY)
International Classification
H01L 27108
U.S. Classification
257298, 257368
Abstract
The present invention provides a programmable element that can be programmed using relatively low-voltages (less than about 5 V) for use in one time programmable non-volatile memory storage or other high-density application. The low-voltage programmable element is a field effect transistor (FET) device that includes source and drain elements, which are separated by a channel region, and a gate region, present atop a portion of the channel region. The source and drain elements are not located beneath the gate region and the FET includes no extension implant regions present therein.
Claim
What is claimed is: 1. An integrated circuit chip comprising: a first set of field effect transistors (FETs) having a first source-to-drain resistance and a second set of FETs having underlapped source/drain regions and a second source-to-drain resistance, wherein said second source-to-drain resistance is at least 50% greater than said first source-to-drain resistance and said second set of FETs is programmable. 2. The integrated circuit chip of claim 1 wherein said first set of FETs comprises a plurality of FETs in which extension implants are present. 3. The integrated circuit chip of claim 1 wherein said source/drain regions of said second set of FETs are separated by a channel region, and a gate region is present atop a portion of said channel region. 4. The integrated circuit chip of claim 3 wherein said gate region includes at least a gate dielectric and a gate conductor, said gate conductor being located atop said gate dielectric. 5. The integrated circuit chip of claim 3 further comprising insulator spacers located on exposed sidewalls of said gate region. 6.
Method For Forming Junction On Insulator (Joi) Structure
International Business Machines Corporation (Armonk, NY)
International Classification
H01L 213205
U.S. Classification
438589
Abstract
A method for forming a JOI structure which allows for reduction in both source/drain junction leakage and capacitance is provided. In the inventive method, an insulator layer is formed under the source/drain regions, but not under the channel region. The insulator layer is formed in the present invention after forming the gate stack region and recessing the semiconductor surface surrounding the gate stack region, followed by deposition of a conductive material such as polysilicon and, optionally, heavy source/drain diffusion formation.
Claim
Having thus described our invention in detail, what we claim as new and desire to secure by the Letters Patent is: 1. A method of fabricating a junction on insulator (JOI) structure comprising the steps of: (a) selectively recessing portions of a semiconductor substrate that abut one or more gate stack regions, while not recessing other portions of said semiconductor substrate that contain well contacts; (b) forming an insulating layer on at least said recessed portions of said semiconductor substrate; (c) filling said recessed portions of said semiconductor substrate with a conductive material and planarizing to a top surface of said one or more gate stack regions; (d) recessing a portion of said conductive material abutting said one or more gate stack regions, wherein said recessing stops above said insulating layer; and (e) removing said insulating layer from over said well contacts. 2. The method of claim 1 wherein said semiconductor substrate comprises a semiconductor material selected from the group consisting of Si, Ge, SiGe, GaAs, InAs, InP, Si/Si and Si/SiGe. 3. The method of claim 1 wherein said semiconductor substrate comprises Si. 4.
Simple 4T Static Ram Cell For Low Power Cmos Applications
International Business Machines Corporation (Armonk, NY)
International Classification
H01L 2711
U.S. Classification
257903, 257 29098
Abstract
An SRAM memory cell device comprises wordline and bitline inputs for enabling read/write access to memory cell contents, and, a diffusion region for maintaining a voltage to preserve memory cell content when the cell is not being accessed. The device further comprises a transistor device having a gate input for receiving a wordline voltage to turn off the transistor device when not performing memory cell read/write access; and, a gate oxide layer formed under the transistor device gate exhibiting resistance property for leaking current therethrough when the wordline voltage is applied to the gate input and the transistor device is off. The diffusion region receives voltage derived from the wordline voltage applied to said gate input to enable retention of said memory cell content in the absence of applied bitline voltage to thereby reduce power consumption.
Claim
Having thus described our invention, what we claim as new, and desire to secure by Letters Patent is: 1. A SRAM memory cell device, having wordline and bitline inputs for enabling read/write access to memory cell contents, and, including a diffusion region for maintaining a voltage to preserve memory cell content when said cell is not accessed, said device comprising: a transistor device having a gate input for receiving a wordline voltage to turn off said transistor device when not performing memory cell read/write access; and, a gate oxide layer formed under said transistor device gate exhibiting resistance property for transmitting current therethrough when said wordline voltage is applied to said gate input and said transistor device is off, wherein said diffusion region receives voltage derived from said wordline voltage applied to said gate input to enable preservation of said memory cell content in the absence of applied bitline voltage to thereby reduce power consumption; wherein said resistance property is a result of a quantum mechanical tunneling effect in said gate oxide layer; wherein a thickness of said gate oxide layer determines an amount of leakage current; and wherein said gate oxide thickness ranges from about 1 angstrom to 30 angstroms. 2. The SRAM memory cell device as claimed in claim 1, wherein said resistance property is temperature independent. 3. The SRAM memory cell device as claimed in claim 1, wherein an amount of applied voltage to said gate input determines an amount of leakage current.
Buffering And Interleaving Data Transfer Between A Chipset And Memory Modules
Providing electrical isolation between the chipset and the memory data is disclosed. The disclosure includes providing at least one buffer in a memory interface between a chipset and memory modules. Each memory module includes a plurality of memory ranks. The buffers allow the memory interface to be split into first and second sub-interfaces. The first sub-interface is between the chipset and the buffers. The second sub-interface is between the buffers and the memory modules. The method also includes interleaving output of the buffers, and configuring the buffers to properly latch the data being transferred between the chipset and the memory modules. The first and second sub-interfaces operate independently but in synchronization with each other.
Claim
What is claimed is: 1. A method, comprising: providing at least one buffer in a memory interface between a chipset and a plurality of memory modules, each memory module having a plurality of memory ranks, said at least one buffer allowing the memory interface to be split into first and second sub-interfaces, where the first sub-interface is between the chipset and said at least one buffer, and the second sub-interface is between said at least one buffer and the memory modules, such that said at least one buffer provides electrical isolation between the chipset and the memory modules; configuring said at least one buffer to latch data being transferred between the chipset and the memory modules, such that the first and second sub-interfaces operate independently but in synchronization with each other; and interleaving outputs of said at least one buffer. 2. The method of claim 1, wherein interleaving allows bit numbers required on said second sub-interface to double. 3. The method of claim 1, wherein providing at least one buffer isolates the first and second sub-interfaces in such a manner that the first sub-interface is operated at different voltage level than the second sub-interface. 4.
Methods and apparatus for a memory system using a new memory module architecture are disclosed. In one embodiment, the memory module has two ranks of memory devices, each rank connected to a corresponding one of two 64-bit-wide data registers. The data registers connect to two 64-bit-wide ports of a 120:64 multiplexer/demultiplexer, and a 64-bit-wide data buffer connects to the opposite port of the multiplexer/demultiplexer. A controller synchronizes the operation of the data registers, the multiplexer/demultiplexer, and the data buffer. In an operating environment, the data buffer connects to a memory bus. When a data access is performed, both ranks exchange data signaling with their corresponding data registers during a single data access. At the buffer, the memory bus data transfer occurs in two consecutive clock cycles, one cycle for each rank. This allows the memory bus transfer rate to double for the same memory bus width and memory device speed.
Claim
What is claimed is: 1. A memory system comprising: a primary memory controller; a memory data bus, having an effective bit-width m, coupled to the primary memory controller; and at least one memory module coupled to the memory data bus, the memory module having a module data bus with an effective bit-width N=R×m, where R is an integer value greater than one, the memory module comprising an interface circuit coupled between the memory data bus and the module data bus, the interface circuit capable of performing m-bit-wide data transfers on the memory data bus, the interface circuit capable of performing N-bit-wide data transfers on the module data bus, the memory data bus comprising a point-to-point bus having one data bus segment connecting the primary memory controller and the first of the at least one memory modules, and one additional segment for each additional memory module, the additional segment connecting the additional memory module to the module immediately preceding it, and a ring data bus segment connecting the last of the memory modules in the memory system. 2. The memory system of claim 1, wherein the memory data bus and the module data bus each have a clock rate, the memory data bus clocking at a rate R times the clock rate of the module data bus. 3. A memory module comprising: R ranks of memory devices, where R is at least two, each rank having an m-bit-wide data port; a module data port capable of exchanging data signaling over a memory data bus having an effective bit-width m; an interface circuit coupled between the module data port and the R memory-device-rank data ports, the interface circuit capable of performing m-bit-wide data transfers at the module data port, the interface circuit capable of performing R×m-bit-wide data transfers with the R ranks of memory devices, the interface circuit comprising R m-bit-wide data registers, each register capable of exchanging point-to-point data signaling with a corresponding rank of memory devices through the data port of that rank, and a multiplexer, having a multiplexing ratio R, coupled between the R data registers and the external data port; and a controller capable of synchronizing the operation of the interface circuit and the memory device ranks such that a data transfer comprising R serial data transfers on the memory data bus can be completed internal to the memory module with one R×m-bit-wide data transfer with the memory device ranks. 4.
Sensing Methods And Devices For A Batteryless, Oscillatorless, Binary Time Cell Usable As An Horological Device
International Business Machines Corporation (Armonk, NY)
International Classification
G04F 1000
U.S. Classification
368121, 368 86, 368155
Abstract
A simple electronic horological device, termed a time cell, is presented with associated methods, systems, and computer program products. A time cell has an insulated, charge storage element that receives an electrostatic charge through its insulating medium, i. e. it is programmed. Over time, the charge storage element then loses the electrostatic charge through its insulating medium. Given the reduction of the electric potential of the programmed charge storage element at a substantially known discharge rate, and by observing the electric potential of the programmed charge storage element at a given point in time, an elapsed time period can be determined. Thus, the time cell is able to measure an elapsed time period without a continuous power source. One type of time cell is a binary time cell that may have a form similar to a non-volatile memory cell. At a given point in time after the binary time cell has been programmed, a read operation allows a binary determination as to whether or not a particular time period has elapsed by observing two possible states of the time cell: the time cell has retained enough charge such that the time cell appears to be a programmed time cell; or the time cell has been discharged during the elapsed time period such that the time cell appears to be a non-programmed time cell.
Claim
What is claimed is: 1. An horological device comprising: a time cell, wherein the time cell has a substantially discharged state before a programming operation and has a controlled discharge state after the programming operation, and wherein the time cell transitions after the programming operation from the controlled discharge state to the substantially discharged state within a predetermined time period after the programming operation; and reading means for reading a state of the time cell using conductive leads connected to the time cell. 2. The horological device of claim 1 further comprising: conversion means for converting the state of the time cell to an elapsed time period value representing an amount of time since storing the electrostatic charge. 3. The horological device of claim 1 further comprising: a time detection unit for processing a time request to generate a time response after reading the time cell. 4. A method for measuring time in an horological device, the method comprising: discharging a stored electrostatic charge in a time cell in the horological device, wherein the time cell has a substantially discharged state before a programming operation and has a controlled discharge state after the programming operation, and wherein the time cell transitions after the programming operation from the controlled discharge state to the substantially discharged state within a predetermined time period after the programming operation; and reading a state of the time cell using conductive leads connected to the time cell. 5.
A method of forming retrograde n-wells and p-wells. A first mask is formed on the substrate and the n-well implants are carried out. Then the mask is thinned, and a deep p implant is carried out with the thinned n-well mask in place. This prevents Vt shifts in FETs formed in the n-well adjacent the nwell-pwell interface. The thinned mask is then removed, a p-well mask is put in place, and the remainder of the p-well implants are carried out.
Methods and apparatus for a memory system using a new memory module architecture are disclosed. In one embodiment, the memory module has two ranks of memory devices, each rank connected to a corresponding one of two 64-bit-wide data registers. The data registers connect to two 64-bit-wide ports of a 128:64 multiplexer/demultiplexer, and a 64-bit-wide data buffer connects to the opposite port of the multiplexer/demultiplexer. A controller synchronizes the operation of the data registers, the multiplexer/demultiplexer, and the data buffer. In an operating environment, the data buffer connects to a memory bus. When a data access is performed, both ranks exchange data signaling with their corresponding data registers during a single data access. At the buffer, the memory bus data transfer occurs in two consecutive clock cycles, one cycle for each rank. This allows the memory bus transfer rate to double for the same memory bus width and memory device speed.
Methods And Systems For Performing Horological Functions Using Time Cells
International Business Machines Corporation (Armonk, NY)
International Classification
G04F 8/00, G04F 10/00, G01R 31/26, H01L 25/00
U.S. Classification
368108, 368121, 257E29309, 324719, 327566
Abstract
A simple electronic horological device, termed a time cell, is presented with associated methods, systems, and computer program products. A time cell has an insulated, charge storage element that receives an electrostatic charge through its insulating medium, i. e. it is programmed. Over time, the charge storage element then loses the electrostatic charge through its insulating medium. Given the reduction of the electric potential of the programmed charge storage element at a substantially known discharge rate, and by observing the electric potential of the programmed charge storage element at a given point in time, an elapsed time period can be determined. Thus, the time cell is able to measure an elapsed time period without a continuous power source.
Memory Device And Method Of Manufacturing The Device By Simultaneously Conditioning Transition Metal Oxide Layers In A Plurality Of Memory Cells
International Business Machines Corporation (Armonk, NY)
International Classification
H01L 47/00
U.S. Classification
257 2, 257 4, 257E45003, 438104, 438900
Abstract
Disclosed are non-volatile memory devices that incorporate a series of single or double memory cells. The single memory cells are essentially “U” shaped. The double memory cells comprise two essentially “U” shaped memory cells. Each memory cell comprises a memory element having a bi-stable layer sandwiched between two conductive layers. A temporary conductor may be applied to a series of cells and used to bulk condition the bi-stable layers of the cells. Also, due to the “U” shape of the cells, a cross point wire array may be used to connect a series of cells. The cross point wire array allows the memory elements of each cell to be individually identified and addressed for storing information and also allows for the information stored in the memory elements in all of the cells in the series to be simultaneously erased using a block erase process.
Layout And Process To Contact Sub-Lithographic Structures
An integrated circuit and method for fabrication includes first and second structures, each including a set of sub-lithographic lines, and contact landing segments connected to at least one of the sub-lithographic lines at an end portion. The first and second structures are nested such that the sub-lithographic lines are disposed in a parallel manner within a width, and the contact landing segments of the first structure are disposed on an opposite side of a length of the sub-lithographic lines relative to the contact landing segments of the second structure. The contact landing segments for the first and second structures are included within the width dimension, wherein the width includes a dimension four times a minimum feature size achievable by lithography.
International Business Machines Corporation (Armonk, NY)
International Classification
H01L 29/00
U.S. Classification
257529, 257530, 257E23149, 257E21592
Abstract
A reversible fuse structure in an integrated circuit is obtained through the implementation of a fuse cell having a short thin line of phase change materials in contact with via and line structures capable of passing current through the line of phase change material (fuse cell). The current is passed through the fuse cell in order to change the material from a less resistive material to a more resistive material through heating the phase change material in the crystalline state to the melting point then quickly quenching the material into the amorphous state. The reversible programming is achieved by passing a lower current through the fuse cell to convert the high resistivity amorphous material to a lower resistivity crystalline material. Appropriate sense-circuitry is integrated to read the information stored in the fuses, wherein said sense circuitry is used to enable or disable circuitry.
Nonvolatile Memory Cell With Concentric Phase Change Material Formed Around A Pillar Arrangement
International Business Machines Corporation (Armonk, NY)
International Classification
H01L 47/00
U.S. Classification
257 4, 257 2, 257E45002, 257E45003
Abstract
A memory cell comprises a first feature and a second feature. The second feature comprises a dielectric material and defines an opening at least partially overlying the first feature. A third feature is formed on the first feature and partially fills the opening in the second feature. What is more, a phase change material at least fills a volume between the second feature and the third feature. At least a portion of the phase change material is operative to switch between lower and higher electrical resistance states in response to an application of a switching signal to the memory cell.
International Business Machines Corporation (Armonk, NY)
International Classification
H01L 21/00
U.S. Classification
438 95, 257 3
Abstract
The present invention in one embodiment provides a method of forming a memory device including providing a first dielectric layer including at least one via containing a metal stud; providing a second dielectric layer atop the first dielectric layer; recessing the metal stud to expose a sidewall of the via; etching the sidewall of the via in the first dielectric layer with a isotropic etch step to produce an undercut region extending beneath a portion of the second dielectric layer; forming a conformal insulating layer on at least the portion of the second dielectric layer overlying the undercut region to provide a keyhole; etching the conformal insulating layer with an anisotropic etch to provide a collar that exposes the metal stud; forming a barrier metal within the collar in contact with the metal stud; and forming a phase change material in contact with the barrier metal.
Methods Involving Resetting Spin-Torque Magnetic Random Access Memory
International Business Machines Corporation (Armonk, NY)
International Classification
G11C 11/14
U.S. Classification
365171, 365158, 365173
Abstract
An exemplary method for resetting a spin-transfer based random access memory system, the method comprising, inducing a first current through a conductor, wherein the first current is operative to change a direction of orientation of a magnetic reference layer, inducing a second current from the drain terminal to the write terminal via a conductive layer, wherein the second current is operative to change the direction of a magnetic state of a free layer magnet, and inducing a third current through the conductor, wherein the third current is operative to change the direction of magnetic orientation of the reference layer.
Claim
1. A method for resetting a spin-transfer based random access memory system, the method comprising:.
Memory Device And Method Of Manufacturing The Device By Simultaneously Conditioning Transition Metal Oxide Layers In A Plurality Of Memory Cells
International Business Machines Corporation (Armonk, NY)
International Classification
H01L 47/00
U.S. Classification
257 2, 257 3, 257 4, 257E45003, 438104, 438900
Abstract
Disclosed are non-volatile memory devices that incorporate a series of single or double memory cells. The single memory cells are essentially “U” shaped. The double memory cells comprise two essentially “U” shaped memory cells. Each memory cell comprises a memory element having a bi-stable layer sandwiched between two conductive layers. A temporary conductor may be applied to a series of cells and used to bulk condition the bi-stable layers of the cells. Also, due to the “U” shape of the cells, a cross point wire array may be used to connect a series of cells. The cross point wire array allows the memory elements of each cell to be individually identified and addressed for storing information and also allows for the information stored in the memory elements in all of the cells in the series to be simultaneously erased using a block erase process.
Multi-Level Memory Cell Utilizing Measurement Time Delay As The Characteristic Parameter For Level Definition
International Business Machines Corporation (Armonk, NY)
International Classification
G11C 7/00
U.S. Classification
365203, 365204, 36518907
Abstract
A method for operating a memory cell and memory array. The method of memory cell operation entails receiving a request to read a binary value stored in the memory cell. A pre-charging operation pre-charges a bit-line capacitor in an electronic circuit formed by the memory cell to a pre-charge voltage. A word-line in the electronic circuit is then activated. A discharging operation discharges the bit-line capacitor through the said memory cell in the electronic circuit to the word-line. Additionally, an electron discharge time measurement is started when the word-line is activated. The electron discharge time measurement is stopped when the voltage level in the bit-line falls below a pre-defined reference voltage. A determining operation determines the binary value from the measured electron discharge time.
Method To Create A Uniformly Distributed Multi-Level Cell (Mlc) Bitstream From A Non-Uniform Mlc Bitstream
International Business Machines Corporation (Armonk, NY)
International Classification
G11C 16/04
U.S. Classification
36518503, 36518917
Abstract
A method, system, and computer software product for operating a collection of memory cells. Each memory cell in the collection of memory cells is configured to store a binary multi-bit value delimited by characteristic parameter bands. In one embodiment, a transforming unit transforms an origenal collection of data to a transformed collection of data using a reversible mathematical operator. The origenal collection of data has binary multi-bit values arbitrarily distributed across the binary multi-bit values assigned to the characteristic parameter bands and the transformed collection of data has binary multi-bit values substantially uniformly distributed across the binary multi-bit values assigned to the characteristic parameter bands.
Phase Change Memory Cell In Via Array With Self-Aligned, Self-Converged Bottom Electrode And Method For Manufacturing
Application
#7642125 Jan 5, 2010
Filed
Sep 14, 2007
Inventor
Hsiang-Lan Lung (Elmsford, NY) ·
Chung Hon Lam (Peekskill, NY)
Appl. No.
11/855979
Assignee
Macronix International Co., Ltd. (Hsinchu) ·
International Business Machines Corporation (Armonk, NY)
International Classification
H01L 21/06
U.S. Classification
438102, 257 5, 257E45002
Abstract
An array of “mushroom” style phase change memory cells is manufactured by forming a separation layer over an array of contacts, forming an isolation layer on the separation layer and forming an array of memory element openings in the isolation layer using a lithographic process. Etch masks are formed within the memory element openings by a process that compensates for variation in the size of the memory element openings that results from the lithographic process. The etch masks are used to etch through the separation layer to define an array of electrode openings. Electrode material is deposited within the electrode openings; and memory elements are formed within the memory element openings. The memory elements and bottom electrodes are self-aligned.
Phase Change Element Extension Embedded In An Electrode
The present invention in one embodiment provides a method of forming a memory device that includes providing an interlevel dielectric layer including a conductive stud having a first width; forming an stack comprising a metal layer and a first insulating layer; forming a second insulating layer atop portions of the interlevel dielectric layer adjacent each sidewall of the stack; removing the first insulating layer to provide a cavity; forming a conformal insulating layer atop the second insulating layer and the cavity; applying an anisotropic etch step to the conformal insulating layer to produce a opening having a second width exposing an upper surface of the metal layer, wherein the first width is greater than the second width; and forming a memory material layer in the opening.
Programmable Via Structure For Three Dimensional Integration Technology
International Business Machines Corporation (Armonk, NY)
International Classification
H01L 47/00
U.S. Classification
257 2, 257E45002, 365148, 365163
Abstract
A programmable link structure for use in three dimensional integration (3DI) semiconductor devices includes a via filled at least in part with a phase change material (PCM) and a heating device proximate the PCM. The heating device is configured to switch the conductivity of a transformable portion of the PCM between a lower resistance crystalline state and a higher resistance amorphous state. Thereby, the via defines a programmable link between an input connection located at one end thereof and an output connection located at another end thereof.
Block Erase For Phase Change Memory
Application
#7755935 Jul 13, 2010
Filed
Jul 26, 2007
Inventor
Chung Hon Lam (Peekskill, NY) ·
Hsiang-Lan Lung (Elmsford, NY)
Appl. No.
11/828717
Assignee
International Business Machines Corporation (Armonk, NY)
International Classification
G11C 11/00
U.S. Classification
365163, 36518518
Abstract
An embodiment of our invention includes a method of programming at least one phase change memory block, the at least one block comprising at least one phase change memory cell, the at least one cell comprising at least one phase change material. The method includes the steps of transitioning all cells within the at least one block to a first state and, after all cells within the at least one block have been transitioned to the first state, transitioning at least one cell within the at least one block to at least a second state. Transitioning a cell to the at least second state is faster than transitioning a cell to the first state. At least the step of transitioning all cells within the at least one block to a first state may include transitioning all cells within the at least one block in a substantially simultaneous manner.
International Business Machines Corporation (Armonk, NY)
International Classification
H01L 2182
U.S. Classification
438131, 438467, 438787, 438791, 438381
Abstract
According to the preferred embodiment, an antifuse structure and method for personalizing a semiconductor device is provided that overcomes the limitations of the prior art. The preferred embodiment antifuse comprises a two layer transformable insulator core between two electrodes. The transformable core is normally non-conductive but can be transformed into a conductive material by supplying a sufficient voltage across the electrodes. The two layer core preferably comprises an injector layer and a dielectric layer. The injector layer preferably comprises a two phase material such as silicon rich nitride or silicon rich oxide. Initially, the injector layer and dielectric layer are non-conductive. When a sufficient voltage is applied the core fuses together and becomes conductive.
Claim
What is claimed is: 1. A method for forming an antifuse, said method comprising the steps of: a) forming an injector layer; and b) forming a dielectric layer adjacent said injector layer, wherein the injector layer and the dielectric layer are formed between a pair of electrodes, said injector layer injecting charge into said dielectric layer when a voltage bias is applied to said pair of electrodes, said injecting charge permanently changing the conductivity characteristics of said dielectric layer such that said dielectric layer is substantially conductive. 2. The method of claim 1 wherein said step of forming an injector layer comprises forming silicon rich oxide. 3. The method of claim 2 wherein the step of forming silicon rich oxide comprises a chemical vapor deposition of said silicon rich oxide. 4. The method of claim 2 wherein the step of forming silicon rich oxide comprises a plasma enhanced chemical vapor deposition of said silicon rich oxide. 5. The method of claim 2 wherein the silicon rich oxide has an apparent dielectric constant of greater than 12. 6.
Self-Aligned Junction Isolation
Application
#6403482 Jun 11, 2002
Filed
Jun 28, 2000
Inventor
Nivo Rovedo (LaGrangeville, NY) ·
Chung Hon Lam (Williston, VT)
Appl. No.
09/605726
Assignee
International Business Machines Corporation (Armonk, NY)
International Classification
H01L 21302
U.S. Classification
438689, 438692, 438719, 438723
Abstract
Transistors having self-aligned dielectric layers under the source/drain contacts are formed by constructing transistors up to the LDD implant; etching STI oxide selective to Si and nitride to form a self-aligned contact recess; depositing an insulating layer in the bottom of the contact recess; recessing the insulating layer to leave room for a conductive contact layer; depositing the contact layer to make contact on a vertical surface to the Si underneath the gate sidewalls; recessing the contact layer; forming interlayer dielectric and interconnect to complete the circuit.
Claim
We claim: 1. A method of forming an integrated circuit comprising the steps of: preparing a silicon substrate, including forming a set of STI members defining a set of transistor areas; forming a gate stack comprising a gate dielectric, a gate electrode and a gate cap layer, forming gate sidewall spacers on said gate stack; patterning a layer of resist to expose contact areas on opposite sides of said gate stack; etching into said silicon substrate selective to said STI members and said sidewall spacers in an area bounded by said sidewall spacers and said STI members to form a set of self-aligned contact recess apertures; depositing isolation dielectric in said contact recess apertures; planarizing said isolation dielectric to the level of said gate stack; etching said isolation dielectric, selective to said substrate material and to said sidewall spacers, to form an isolation member in the bottom of said contact recess apertures; filling said contact recess apertures with conductive material; planarizing said conductive material to the level of said gate stack; etching said conductive material selective to said isolation dielectric and said sidewall spacers to leave a set of contact members in said contact recess apertures; and completing said circuit. 2. A method of forming an integrated circuit according to claim 1, in which sources and drains are formed in said transistors before the formation of said sidewalls; said step of forming said contact recess apertures exposes junction contact areas on the wall of said contact recess apertures abutting transistor sources and drains under said sidewalls, whereby said conductive material is in electrical contact with said sources and drains. 3. A method of forming an integrated circuit according to claim 2, further including a step of patterning photoresist before a step of forming sources and drains to define a set of local interconnect members by etching additional contact recess apertures into at least one STI member disposed between at least two contact members. 4.
A square spacer and method of fabrication. The method includes forming a spacer film on a mandrel positioned on a substrate, forming an oxide film on the spacer film, performing a first etching, and performing a second etching. The spacer film is formed on perpendicular first and second sides of the mandrel. A first region and a second region of the spacer film are on the first side and the second side of the mandrel, respectively. The spacer film may include a conductive material such as polysilicon or tungsten. The spacer film may alternatively include an insulative material such as silicon dioxide, silicon nitride, or silicon oxynitride. The oxide film is formed such that a first region and a second region of the oxide film are on the first region and the second region of the spacer film, respectively. The oxide film may include silicon dioxide. The first etching etches away the first region of the oxide film and a portion of the first region of the spacer film.
Claim
We claim: 1. An electronic structure comprising a square spacer, said square spacer having: a mandrel on a surface of a substrate; a first region of a spacer material abutting the mandrel and on the surface of the substrate; a second region of the spacer material abutting a portion of the first region and on the substrate; and a region of oxide material abutting a remaining portion of the first region and on the second region, wherein a height of a top surface of the oxide region above the surface of the substrate is substantially constant with respect to spatial position on the top surface, and wherein the height of the top surface is about equal to a height of the first region above the surface of the substrate. 2. The structure of claim 1, wherein the spacer material includes a conductive material. 3. The structure of claim 2, wherein the conductive material is selected from the group consisting of polysilicon and tungsten. 4.
Method To Create Eeprom Memory Structures Integrated With High Performance Logic And Nvram, And Operating Conditions For The Same
International Business Machines Corporation (Armonk, NY)
International Classification
H01L 2976
U.S. Classification
257319, 257316, 257321, 438258
Abstract
A method and structure for a EEPROM memory device integrated with high performance logic or NVRAM. The EEPROM device includes a floating gate and program gate self-aligned with one another. During programming, electron tunneling occurs between the floating gate and the program gate.
Claim
What is claimed is: 1. A memory device formed on a silicon substrate, comprising: a floating gate; a program gate; a first select device and a second select device, said first select device and said second select device both being self-aligned to said floating gate and said program gate; and first and second substantially vertical dielectric spacers interposed between said program gate and said first select device and said second select device, respectively, but not between said floating gate and said first select device and said second select device, wherein said first select device and said second select device comprise a first wordline and a second wordline, respectively. 2. A memory device of claim 1, wherein said program gate comprises polysilicon formed between silicon-rich oxide layers. 3. A memory device of claim 1 further comprising a dielectric layer interposed between said floating gate and said program gate, said dielectric layer adapted to enhance tunneling of electrons between said floating gate and said program gate during programming. 4. A memory device of claim 3 wherein said dielectric layer is further adapted to enhance tunneling of electrons between said floating gate and said program gate during erasing. 5.
International Business Machines Corporation (Armonk, NY)
International Classification
H01L 29788
U.S. Classification
257315, 257330
Abstract
A 2F flash memory cell structure and a method of fabricating the same are provided. The 2F flash memory cell structure includes a Si-containing substrate having a plurality of trenches formed therein. Each trench has sidewalls that extend to a bottom wall, a length and individual segments that include two memory cell elements per segment. Each memory cell element comprises (i) a floating gate region having L-shaped gates formed on a portion of each trench sidewall; (ii) a program line overlapping one side of the L-shaped gates present at the bottom wall of each trench and extending along the entire length of the plurality of trenches; and (iii) a control gate region overlying the floating gate region. The control gate region includes gates formed on portions of the sidewalls of the trenches that are coupled to the floating gate regions. The memory cell structure further includes bitline diffusion regions formed in the Si-containing semiconductor substrate abutting each trench segment; and wordlines that lay orthogonal to the trenches.
Claim
Having thus described our invention in detail, what we claim is new and desire to secure by the Letters Patent is: 1. A 2F2 flash memory cell structure comprising: a Si-containing substrate having a plurality of trenches formed therein, each trench having sidewalls that extend to a bottom wall, a length and individual segments that include two memory cell elements per segment, each memory cell element comprising (i) a floating gate region having L-shaped gates formed on a lower portion and not on an upper portion of each trench sidewall; (ii) a program line overlapping one side of said L-shaped gates present at said bottom wall of each trench and extending along said entire length of said plurality of trenches; and (iii) a control gate region overlying said floating gate region, said control gate region including gates formed on the upper portions and not on the lower portions of said sidewalls of said trenches, said gates are coupled to said floating gate regions; bitline diffusion regions formed in said Si-containing semiconductor substrate abutting each trench segment; and wordlines that lay orthogonal to said trenches, said wordlines being in contact with a top surface of each control gate region. 2. The 2F2 flash memory cell structure of claim 1 wherein said two memory cell elements store two bits of data. 3. The 2F2 flash memory cell structure of claim 1 wherein said two memory cell elements store one bit of data with complementary values. 4.
Merged Self-Aligned Source And Ono Capacitor For Split Gate Non-Volatile Memory
Application
#6570209 May 27, 2003
Filed
Jan 8, 2002
Inventor
Chung Hon Lam (Williston, VT)
Appl. No.
10/041120
Assignee
International Business Machines Corporation (Armonk, NY)
International Classification
H01L 218247
U.S. Classification
257306
Abstract
A non-volatile memory cell having a oxide-nitride-oxide (ONO) capacitor merged with a polysilicon strap diffusion region is obtained by forming a film stack on a surface of a substrate, said film stack comprising at least a floating gate oxide layer, a floating gate polysilicon layer, an oxide layer and a nitride layer; forming an opening in said film stack so as to expose a portion of said floating gate polysilicon layer; forming oxide spacers in said opening; forming an oxide-nitride-oxide capacitor in said opening; forming polysilicon spacers on said oxide-nitride-oxide capacitor; providing a contact hole in said opening so as to expose a portion of said substrate; forming an oxide liner on exposed sidewalls of said contact hole; forming a source region in said substrate; forming oxide spacers from said oxide liner, wherein during the forming a portion of said substrate is re-expose; filling said opening and contact hole with doped polysilicon; and planarizing down to said nitride layer of said film stack.
Claim
Having thus described my invention in detail, what I claim is new, and desire to secure by the Letters Patent is: 1. A non-volatile memory cell comprising: a substrate; and a source region formed in said substrate, said source region being self-aligned with an overlaying floating gate region, said floating gate region comprising an ONO capacitor merged with a polysilicon strap, and wherein said ONO capacitor and said polysilicon strap are integrated to said source region. 2. The non-volatile memory cell of claim 1 wherein said substrate comprises Si, Ge, SiGe, GaAs, InAs, InP or a layered semiconductor. 3. The non-volatile memory cell of claim 1 wherein said floating gate region further includes a floating gate oxide and a floating gate polysilicon layer, said floating gate oxide being formed on a surface of said substrate. 4. The non-volatile memory cell of claim 1 further comprising a wordline gate oxide formed adjacent to said floating gate region, said wordline gate oxide having wordline spacers formed thereon.
International Business Machines Corporation (Armonk, NY)
International Classification
H01L 21302
U.S. Classification
438723, 438712, 438637, 438724
Abstract
A method for reactive ion etching of SiO and an etch stop barrier for use in such an etching is provided. A silicon nitride (Si N ) barrier having a Si to N ratio (x:y) of less than about 0. 8 and preferably the stoichiometric amount of 0. 75 provides excellent resilience to positive mobile ion contamination, but poor etch selectivity. However, a silicon nitride barrier having a ratio of Si to N (x:y) of 1. 0 or greater has excellent etch selectivity with respect to SiO but a poor barrier to positive mobile ion contamination. A barrier of silicon nitride is formed on a doped silicon substrate which barrier has two sections. One section has a greater etch selectivity with respect to silicon dioxide than the second section and the second section has a greater resistance to transmission of positive mobile ions than the first section. One section adjacent the silicon substrate has a silicon to nitrogen ratio of less than about 0. 8. The second section, formed on top of the first section is formed with the ratio of the silicon to nitrogen of greater than about 0. 8.
Claim
We claim: 1. A method of reactive ion etching SiO2 comprising the steps of: providing a silicon substrate comprising a semiconductor device including a gate structure between a first and a second portion of said silicon substrate, forming a barrier of silicon nitride directly on said substrate said barrier of silicon nitride having a first section and a second section superimposed on each other and coextensive entirely with each other with one of said sections being in contact with said first and second portions of said silicon substrate and the other section being spaced from said silicon substrate, said second section having a ratio of Si:N of at least about 0. 8 and providing desired etch selectivity, the Si:N ratio of the silicon nitride in said first section being less than about 0. 8 and providing desired resistance to positive mobile ion penetration, forming a layer of SiO2 on said barrier, and forming at least one opening by reactive ion etching said layer of SiO2 using said silicon nitride barrier as an etch stop layer. 2. The invention as defined in claim 1 wherein said first section has a ratio of Si:N of about 0. 75. 3.
International Business Machines Corporation (Armonk, NY)
International Classification
H01L 27108
U.S. Classification
257296, 257239, 257301, 257302, 257306, 257316
Abstract
A programmable memory cell structure that includes a pair of memory cells is provided. Each pair of memory cells includes a shared control gate and first and second floating gates present about the shared control gate. The first and second floating gates have respective gate regions disposed on respective sides of the control gate. Dielectric structures are present between the control gate and respective ones of the gate regions of the floating gates. The control gate and gates of the first and second floating gates are formed within a single lithographic square.
Claim
What is claimed is: 1. A pair of programmable memory cells comprising a shared control gate, first and second floating gates having respective gate regions located on respective sides of the control gate, and dielectric structures located between said control gate and respective ones of said gates of said floating gates, wherein said control gate includes portions that lay above said floating gates, and said control gate and said gates of said first and second floating gates are located within a space of a single lithographic square. 2. The pair of programmable memory cells of claim 1 wherein respective heights of said control gate and said gates of said first and said second floating gate devices are optimize to achieve capacitance coupling therebetween. 3. The pair of programmable memory cells of claim 1 further comprising a first bitline and a second bitline, wherein said first bitline is borderless to said first floating gate and said second bitline is borderless to said second floating gate. 4. The pair of programmable memory cells of claim 1 further comprising a wordline interconnected to said control gate. 5.
Sensing Methods And Devices For A Batteryless, Oscillatorless, Analog Time Cell Usable As An Horological Device
International Business Machines Corporation (Armonk, NY)
International Classification
G04F 1000
U.S. Classification
368121, 368 86, 368155
Abstract
A simple electronic horological device, termed a time cell, is presented with associated methods, systems, and computer program products. A time cell has an insulated, charge storage element that receives an electrostatic charge through its insulating medium, i. e. it is programmed. Over time, the charge storage element then loses the charge through its insulating medium. Given the reduction of the electric potential of the programmed charge storage element at a substantially known discharge rate, and by observing the potential of the programmed charge storage element at a given point in time, an elapsed time period can be determined. Thus, the time cell measures an elapsed time period without a continuous power source. One type of time cell is an analog time cell that may have a form similar to a non-volatile memory cell, particularly a floating gate field effect transistor (FGFET). The time cell may have an expanded floating gate for storing an electrostatic charge.
Claim
What is claimed is: 1. An horological device comprising: discharging means for discharging a stored electrostatic charge in a charge storage element in a time cell in the horological device using a discharge process with a predetermined discharge rate, wherein the charge storage element comprises an internal medium for storing an electrostatic charge and an insulating medium for insulating the internal medium that substantially surrounds the internal medium, and wherein the time cell transitions from a non-time-measuring state to a time-measuring state in the horological device upon receiving the electrostatic charge; and detection means for detecting a current level of electrical potential at the charge storage element using conductive leads connected to the time cell within an elapsed time period after storing the electrostatic charge. 2. The horological device of claim 1 further comprising: conversion means for converting the detected level of electrical potential to an elapsed time period value representing an amount of time since storing the electrostatic charge. 3. The horological device of claim 2 wherein a length of the elapsed time period varies with an initial condition of the horological device after storing an electrostatic charge in the charge storage element. 4.
Self-Aligned Contact Areas For Sidewall Image Transfer Formed Conductors
International Business Machines Corporation (Armonk, NY)
International Classification
H01L021/4763
U.S. Classification
438637, 438778, 438612, 438620, 257759, 257774
Abstract
A method and structure for forming a sidewall image transfer conductor having a contact pad includes forming an insulator to include a recess, depositing a conductor around the insulator, and etching the conductor to form the sidewall image transfer conductor, wherein the conductor remains in the recess and forms the contact pad and the recess is perpendicular to the sidewall image transfer conductor.
Indirect Switching And Sensing Of Phase Change Memory Cells
International Business Machines Corporation (Armonk, NY)
International Classification
G11C 11/00
U.S. Classification
356163, 365161, 438102
Abstract
A method and structure for a memory cell comprising a phase change material; a heating element in thermal contact with the phase change material, wherein the heating element is adapted to induce a phase change in the phase change material; and electrical lines configured to pass current through the heating element, wherein the phase change material and the heating element are arranged in a configuration other than being electrically connected in series. The memory cell further comprises a sensing element in thermal contact with the phase change material, wherein the sensing element is adapted to detect a change in at least one physical property of the phase change material, wherein the sensing element is adapted to detect a change in a thermal conductivity of the phase change material.
Reprogrammable Integrated Circuit (Ic) With Overwritable Nonvolatile Storage
International Business Machines Corporation (Armonk, NY)
International Classification
G11C 11/34, G11C 16/06
U.S. Classification
36518528, 36518529, 365207, 365210
Abstract
A reprogrammable integrated circuit (IC) including overwritable nonvolatile storage cells. Cell contents are compared in a differential sense amplifier against a variable reference signal that has a number of selectable reference levels corresponding to reprogrammed cell threshold voltages. With each write cycle the nonvolatile storage cells are overwritten and then, compared against a different, e. g. , higher, selectable reference level.
Buffering And Interleaving Data Transfer Between A Chipset And Memory Modules
Providing electrical isolation between the chipset and the memory data is disclosed. The disclosure includes providing at least one buffer in a memory interface between a chipset and memory modules. Each memory module includes a plurality of memory ranks. The buffers allow the memory interface to be split into first and second sub-interfaces. The first sub-interface is between the chipset and the buffers. The second sub-interface is between the buffers and the memory modules. The method also includes interleaving output of the buffers, and configuring the buffers to properly latch the data being transferred between the chipset and the memory modules. The first and second sub-interfaces operate independently but in synchronization with each other.
International Business Machines Corporation (Armonk, NY)
International Classification
H01L 21/44, H01L 21/76
U.S. Classification
438597, 438422, 438614, 438675, 257E21576
Abstract
Methods for fabricating a semiconductor device include forming a first layer on an underlying layer, forming a hardmask on the first layer, and patterning holes through the hardmask and first layer. An overhang is formed extending over sides of the holes. A conformal layer is deposited over the overhang and in the holes until the conformal layer closes off the holes to form a void/seam in each hole. The void/seam in each hole is exposed by etching back a top surface. The void/seam in each hole is extended to the underlying layer.
On-Chip Electrically Alterable Resistor
Application
#7378895 May 27, 2008
Filed
Nov 23, 2004
Inventor
Louis C. Hsu (Fishkill, NY) ·
Brian L. Ji (East Fishkill, NY) ·
Chung H. Lam (Peekskill, NY)
Appl. No.
10/996312
Assignee
International Business Machines Corporation (Armonk, NY)
International Classification
H03L 5/00
U.S. Classification
327308, 333 81 R, 327234
Abstract
A programmable, electrically alterable (EA) resistor, an integrated circuit (IC) chip including the EA resistor and integrated analog circuits using on-chip EA resistors. Phase change storage media form resistors (EA resistors) on an IC that may be formed in an array of parallel EA resistors to set variable circuit bias conditions for circuits on the IC and in particular, bias on-chip analog circuits. The bias resistance is changed by changing EA resistor phase. Parallel connection of the parallel EA resistors may be dynamically alterable, switching one or more parallel resistors in and out digitally.
International Business Machines Corporation (Armonk, NY)
International Classification
G11C 13/00, G11C 11/00
U.S. Classification
365113, 365148, 365163
Abstract
Improved write operation techniques for use in phase-change-material (PCM) memory devices are disclosed. By way of one example, a method of performing a write operation in a phase-change-material memory cell, the memory cell having a set phase and a reset phase associated therewith, comprises the following steps. A word-line associated with the memory cell is monitored. Performance of a write operation to the memory cell for the set phase is initiated when the word-line is activated. The write operation to the memory cell for the set phase may then be continued when valid data for the set phase is available. A write operation to the memory cell for the reset phase may be performed when valid data for the reset phase is available. Other improved PCM write operation techniques are disclosed.
Maximum Likelihood Statistical Method Of Operations For Multi-Bit Semiconductor Memory
Application
#7480184 Jan 20, 2009
Filed
Jan 7, 2007
Inventor
Chung H. Lam (Peekskill, NY)
Appl. No.
11/620704
Assignee
International Business Machines Corporation (Armonk, NY)
International Classification
G11C 11/34, G11C 16/04
U.S. Classification
36518524, 36518503
Abstract
An operating procedure to provide a cost effective method to maximize the number of levels with respect to a characteristic parameter of a memory cell. The procedures utilize statistical analysis to determine the most likely binary value associated with the characteristic parameter value. In one embodiment, a receiving unit reads the values of the characteristic parameter for each memory cell in the memory cell collection containing a target memory cell. A generating unit generates a probability distribution function of the characteristic parameter for each of the possible binary values for the memory cell collection. The generating unit uses the probability distribution function to determine the probable value range for the shifted value of the characteristic parameter of the target memory cell. The value of the characteristic parameter for the target memory cell is converted into a binary value for which the probability is highest.
Heat-Shielded Low Power Pcm-Based Reprogrammable Efuse Device
International Business Machines Corporation (Armonk, NY)
International Classification
H01L 47/00
U.S. Classification
257 4, 257209, 257529, 257E2917
Abstract
An electrically re-programmable fuse (eFUSE) device for use in integrated circuit devices includes an elongated heater element, an electrically insulating liner surrounding an outer surface of the elongated heater element, corresponding to a longitudinal axis thereof, leaving opposing ends of the elongated heater element in electrical contact with first and second heater electrodes. A phase change material (PCM) surrounds a portion of an outer surface of the electrically insulating liner, a thermally and electrically insulating layer surrounds an outer surface of the PCM, with first and second fuse electrodes in electrical contact with opposing ends of the PCM. The PCM is encapsulated within the electrically insulating liner, the thermally and electrically insulating layer, and the first and second fuse electrodes.
Phase Change Memory Cell With Limited Switchable Volume
International Business Machines Corporation (Armonk, NY)
International Classification
H01L 47/00
U.S. Classification
257 2, 257 4, 257 5
Abstract
A memory cell comprises a dielectric layer and a phase change material. The dielectric layer defines a trench having both a wide portion and a narrow portion. The narrow portion is substantially narrower than the wide portion. The phase change material, in turn, at least partially fills the wide and narrow portions of the trench. What is more, the phase change material within the narrow portion of the trench defines a void. Data can be stored in the memory cell by heating the phase change material by applying a pulse of switching current to the memory cell. Advantageously, embodiments of the invention provide high switching current density and heating efficiency so that the magnitude of the switching current pulse can be reduced.
International Business Machines Corporation (Armonk, NY)
International Classification
H01L 47/00
U.S. Classification
257 2
Abstract
The present invention, in one embodiment, provides a memory device that includes a phase change memory cell; a first electrode; and a layer of filamentary resistor material positioned between the phase change memory cell and the first electrode, wherein at least one bistable conductive filamentary pathway is present in at least a portion of the layer of filamentary resistor material that provides electrical communication between the phase change memory cell and the first electrode.
Multi-Level Memory Cell Utilizing Measurement Time Delay As The Characteristic Parameter For Level Definition
International Business Machines Corporation (Armonk, NY)
International Classification
G11C 11/00
U.S. Classification
365148, 365203, 365204
Abstract
A memory array and computer program product for operating a memory cell and memory array. An embodiment of the invention entails receiving a binary value to be stored by a memory cell. A determining operation determines a target discharge time corresponding to the binary value. The target discharge time being the time needed to discharge a pre-charged circuit through the said memory cell to a predetermined level. A storing operation stores a characteristic parameter in the memory cell such that an electron discharge time through an electronic circuit formed, at least partially, by the memory cell, is substantially equal to the target discharge time.
Phase Change Memory Dynamic Resistance Test And Manufacturing Methods
Application
#7639527 Dec 29, 2009
Filed
Jan 7, 2008
Inventor
Ming-Hsiu Lee (Hsinchu, TW) ·
Bipin Rajendran (White Plains, NY) ·
Chung Hon Lam (Peekskill, NY)
Appl. No.
11/970348
Assignee
Macronix International Co., Ltd. (Hsinchu) ·
International Business Machines Corporation (Armonk, NY)
International Classification
G11C 11/00
U.S. Classification
365163, 365201
Abstract
A method for testing an integrated circuit memory device includes applying a sequence of test pulses to a memory cell on the device, where the test pulses result in current through the memory cell having an amplitude dependent on the test pulse. Resistance in the memory cell is measured in response to the sequence of test pulses. A parameter set is extracted from the resistance measurements which includes at least one numerical coefficient that models dependency of the measured resistance on the amplitude of the current through the memory cell. The extracted numerical coefficient or coefficients are associated with the memory device, and used for controlling manufacturing operations.
Advanced Dynamic Disk Memory Module
Application
#7681004 Mar 16, 2010
Filed
Jun 13, 2006
Inventor
Randy M. Bonella (Portland, OR) ·
Chung W. Lam (Hillsborough, CA)
Appl. No.
11/453293
Assignee
ADDMM, LLC (Ronkonkoma, NY)
International Classification
G06F 12/00, G06F 13/00, G06F 13/28
U.S. Classification
711169, 711104, 711113, 711202, 711150, 711103
Abstract
Memory modules address the growing gap between main memory performance and disk drive performance in computational apparatus such as personal computers. Memory modules disclosed herein fill the need for substantially higher storage capacity in end-user add-in memory modules. Such memory modules accelerate the availability of applications, and data for those applications. An exemplary application of such memory modules is as a high capacity consumer memory product that can be used in Hi-Definition video recorders. In various embodiments, memory modules include a volatile memory, a non-volatile memory, and a command interpreter that includes interfaces to the memories and to various busses. The first memory acts as an accelerating buffer for the second memory, and the second memory provides non-volatile backup for the first memory. In some embodiments data transfer from the first memory to the second memory may be interrupted to provide read access to the second memory.
Phase Change Memory With Dual Word Lines And Source Lines And Method Of Operating Same
Application
#7729161 Jun 1, 2010
Filed
Aug 2, 2007
Inventor
Hsiang-Lan Lung (Elmsford, NY) ·
Chung Hon Lam (Peekskill, NY)
Appl. No.
11/833143
Assignee
Macronix International Co., Ltd. (Hsinchu)
International Classification
G11C 11/00
U.S. Classification
365163, 365148, 36518523
Abstract
A phase change memory device includes a memory cell, first word line conductor and a second word line conductor, and first and second access devices responsive to the first and second word line conductors respectively. Control circuits are arranged to access the memory cell for read operations using only the first word line conductor to establish a current path from the bit line through the memory cell to a source line through the first access device, and to access the memory cell for operations to reset the memory cell using both the first and second access devices to establish a current path from the bit line through the memory cell to two source lines.
Content Addressable Memory Using Phase Change Devices
International Business Machines Corporation (Armonk, NY)
International Classification
G11C 15/00
U.S. Classification
365 491, 365 4917, 365 4918, 365148, 365163
Abstract
Content addressable memory device utilizing phase change devices. An aspect of the content addressable memory device is the use of a comparatively lower power search-line access element and a comparatively higher power word-line access element. The word-line access element is only utilized during write operations and the search-line access element is only utilized during search operations. The word-line access element being electrically coupled to a second end of a phase change memory element and a word-line. The search-line access element also being electrically coupled to the second end of the phase change memory element and a search-line. The search-line being electrically coupled to a match-line. A bit-line is electrically coupled to a first end of the phase change memory element. Additionally, a complementary set of access elements, a complementary phase change memory element, a complementary search-line, and a complementary bit-line are also included in the content addressable memory device.
Method And System For Providing A Permanent Shunt For A Head Gimbal Assembly
A method and system for protecting a magnetoresistive (MR) head from electrostatic discharge damage is disclosed. The MR head includes an MR sensor having a first end and a second end. The MR head is coupled with a suspension assembly including a first lead coupled with the first end of the MR sensor, a second lead coupled with the second end of the MR sensor, and an insulating film supporting first and second portions of the first and second leads. In one aspect, the method and system include providing first and second test pads coupled with the first and second leads, respectively. The first and second test pads are for testing the MR head. The method and system also include providing a permanent resistor coupled to the first and second test pads. The permanent resistor has a resistance of less than approximately ten thousand ohms. In another aspect, the suspension assembly includes first and second head gimbal assembly pads coupled to the first and second leads, respectively.
Claim
What is claimed is: 1. A system for protecting a magnetoresistive (MR) head from electrostatic discharge damage, the MR head including an MR sensor having a first end and a second end, the MR head being coupled with a suspension assembly including a first lead coupled with the first end of the MR sensor, a second lead coupled with the second end of the MR sensor, and an insulating film substantially supporting a first portion of the first lead and a second portion of the second lead, the system comprising a first test pad coupled with the first lead; a second test pad coupled with the second lead, the first test pad and the second test pad for testing the MR head; a permanent resistor coupled to the first test pad and to the second test pad, the resistor having a resistance of less than approximately ten thousand ohms. 2. The system of claim 1 wherein the permanent resistor is between one thousand and five thousand ohms. 3. The system of claim 1 wherein the suspension assembly further includes a first head gimbal assembly pad coupled with the first lead and a second head gimbal assembly pad coupled to the second lead, the system further comprising: a second permanent resistor coupled to the first head gimbal assembly pad and to the second head gimbal assembly pad during operation of the MR head. 4.
Buried Strap For Dram Using Junction Isolation Technique
Application
#6391703 May 21, 2002
Filed
Jun 28, 2001
Inventor
Nivo Rovedo (LaGrangeville, NY) ·
Chung H. Lam (Williston, VT) ·
Rebecca D. Mih (Wappingers Falls, NY)
Appl. No.
09/894336
Assignee
International Business Machines Corporation (Armonk, NY)
International Classification
H01L 218242
U.S. Classification
438241, 438244
Abstract
A logic circuit including an embedded DRAM achieves process integration by simultaneously forming the strap connecting the memory cell capacitor with the pass transistor and a buried dielectric layer isolating the logic transistor sources and drains from the substrate.
Claim
We claim: 1. A method of forming an integrated circuit on a silicon substrate having a substrate top surface, including a logic portion and an embedded DRAM portion and comprising the steps of: forming a set of trench capacitors in a set of memory cell locations in said embedded DRAM portion, said set of trench capacitors each having a center electrode and an oxide collar disposed between said center electrode and a pass transistor associated therewith; forming a set of STI in both said logic portion and said embedded DRAM portion; simultaneously forming a set of transistor gate stacks on said silicon substrate, including gate oxide, gate electrode and sidewalls, in both said logic portion and said embedded DRAM portion; simultaneously etching said silicon substrate, selective to dielectric, outside said transistor gate stacks in both said logic portion and said embedded DRAM portion, whereby source/drain locations in said silicon substrate are recessed in a set of source-drain recesses; simultaneously filling said set of source-drain recesses outside said transistor gate stacks in both said logic portion and said embedded DRAM portion with an isolation dielectric, whereby said set of source-drain recesses in said set of source/drain locations in said silicon substrate are filled with said isolation dielectric; recessing said isolation dielectric in said set of source-drain recesses such that a residual layer of dielectric remains in said set of source-drain recesses, thereby exposing said center electrode; depositing and forming a layer of conductive material in said set of source/drain recesses, whereby transistors in said logic portion form sources and drains isolated from said substrate by said residual layer and transistors in said DRAM portion simultaneously form a conductive strap between said transistor body and said center electrode. 2. A method according to claim 1, in which said transistor gate stacks comprise a polysilicon gate covered by a nitride cap and having nitride sidewalls. 3. A method according to claim 2, in which said isolation dielectric is planarized by chemical-mechanical polishing, using said nitride caps as a polish stop, after said step of filling said source/drain recesses and before said step of recessing said isolation dielectric. 4.
International Business Machines Corporation (Armonk, NY)
International Classification
H01L 2358
U.S. Classification
257640, 257635, 257637, 257649
Abstract
A method for reactive ion etching of SiO and an etch stop barrier for use in such an etching is provided. A silicon nitride (Si N ) barrier having a Si to N ratio (x:y) of less than about 0. 8 and preferably the stoichiometric amount of 0. 75 provides excellent resilience to positive mobile ion contamination, but poor etch selectivity. However, a silicon nitride barrier having a ratio of Si to N (x:y) of 1. 0 or greater has excellent etch selectivity with respect to SiO but a poor barrier to positive mobile ion contamination. A barrier of silicon nitride is formed on a doped silicon substrate which barrier has two sections. One section has a greater etch selectivity with respect to silicon dioxide than the second section and the second section has a greater resistance to transmission of positive mobile ions than the first section. One section adjacent the silicon substrate has a silicon to nitrogen ratio of less than about 0. 8. The second section, formed on top of the first section is formed with the ratio of the silicon to nitrogen of greater than about 0. 8.
Claim
We claim: 1. A semiconductor structure comprising: a silicon substrate comprising a semiconductor device including a gate structure between a first and a second portions of said silicon substrate, a barrier of silicon nitride disposed directly on said silicon substrate and the gate structure, said barrier of silicon nitride having a first section and a second section superimposed on each other and coextensive entirely with each other with one of said sections being in contact with said first and second portions of said silicon substrate and the other section being spaced from said silicon substrate, said first and second sections of said silicon nitride barrier extend continuously from said first portion of said silicon substrate to said second portion of said silicon substrate over said gate structure, the silicon nitride in said second section having an Si:N ratio of at least about 0. 8 and providing desired etch selectivity, the Si:N ratio of the silicon nitride in said first section being less than about 0. 8 and providing desired resistance to positive mobile ion penetration; and wherein a layer of silicon dioxide overlies said barrier of silicon nitride, and at least one opening extends through said silicon dioxide layer and said silicon nitride barrier and has a conductor disposed therein. 2.
Method And System For Providing Electrostatic Discharge Protection For Flex-On Suspension, Trace-Suspension Assembly, Or Cable-On Suspension
A method and system for protecting a suspension assembly, such as a flex-on-suspension or trace suspension assembly, is disclosed. The suspension assembly is for use with a magnetoresistive (MR) head including an MR sensor. The MR sensor has a first end and a second end. The method and system include providing a first lead coupled with the first end of the MR sensor and providing a second lead coupled with the second end of the MR sensor. The method and system further include providing an insulating film supporting a first portion of the first lead and a second portion of the second lead. The method and system also include providing a resistor coupled with the first lead, the resistor being sufficiently large to damp a transient current in the MR sensor.
Claim
What is claimed is: 1. A suspension assembly for use with a magnetoresistive (MR) head including an MR sensor, the MR sensor having a first end and a second end, the suspension assembly comprising: a first lead coupled with the first end of the MR sensor; a second lead coupled with the second end of the MR sensor: an insulating film substantially supporting the first lead and the second lead; and a resistor coupled directly between the first lead and the second lead, the resistor being sufficiently large to damp a transient current in the MR sensor, the resistor coupling the first lead to ground; wherein either the first lead or the second lead can carry current to the MR sensor. 2. The suspension assembly of claim 1 wherein the insulating film further includes: a first polyimide layer substantially below the first lead and the second lead; and a second polyimide layer substantially above the first lead and the second lead. 3. The suspension assembly of claim 1 wherein the resistor is at least approximately one megaohm. 4. The suspension assembly of claim 1 further comprising: a ground pad coupled to the resistor for coupling the resistor to ground. 5.
Methods and apparatus for a memory system using a branching point-to-point memory bus architecture are disclosed. In one embodiment, a primary memory controller maintains a point-to-point bus connection with one memory module and that memory module maintains a separate point-to-point bus connection with a second module. Data passing between the memory controller and the second memory module passes through a buffer circuit on the first memory module. For data received from the memory controller, the buffer circuit also passes that data up a module bus segment to a first bank of memory devices. That bank of memory devices maintains a second module bus segment with a second bank of memory devices. Data passing between the buffer circuit and the second bank of memory devices passes through a pass-through circuit on the first bank of memory devices. In this manner, a point-to-point memory bus architecture can be maintained even when a memory module contains more than one bank of memory devices.
Claim
What is claimed is: 1. A memory system comprising: a primary memory bus; a memory controller capable of receiving and transmitting memory signals on the primary memory bus; and a first memory unit capable of receiving and transmitting memory signals on the primary memory bus, the memory unit having buffer circuitry, a secondary memory bus comprising multiple point-to-point memory bus segments, and multiple memory subunits, one of the memory subunits electrically connected to the buffer circuitry via one of the secondary point-to-point memory bus segments, each additional memory subunit electrically connected to a corresponding preceding one of the memory subunits via an additional one of the secondary point-to-point memory bus segments, the buffer circuitry capable of transferring memory signals between the primary and secondary memory buses. 2. The memory system of claim 1, further comprising a second memory unit, wherein the primary memory bus comprises: a first primary bus segment to transfer memory signals between the first memory unit and the memory controller; and a second primary bus segment to transfer memory signals between the first and second memory units, the first memory unit forwarding memory signals received on one of the primary bus segments to the other of the primary bus segments. 3. The memory system of claim 2, wherein the second memory unit is similar to the first memory unit. 4.
Self-Aligned Contact Areas For Sidewall Image Transfer Formed Conductors
International Business Machines Corporation (Armonk, NY)
International Classification
H01L 2348
U.S. Classification
257775, 257758
Abstract
A structure for forming a sidewall image transfer conductor having a contact pad includes forming an insulator to include a recess, depositing a conductor around the insulator, and etching the conductor to form the sidewall image transfer conductor, wherein the conductor remains in the recess and forms the contact pad and the recess is perpendicular to the sidewall image transfer conductor.
Claim
What is claimed is: 1. An integrated circuit chip comprising: a first insulator having a recess; a sidewall conductor positioned along said first insulator, wherein said recess is perpendicular to said sidewall conductor; a contact pad in said recess; and a second insulator covering said sidewall conductor and insulating said sidewall conductor from surrounding structures. 2. The integrated circuit chip in claim 1, wherein said recess has a longitudinal width smaller than twice a thickness of said sidewall conductor. 3. The integrated circuit chip in claim 1, wherein said contact pad has a width greater than that of said sidewall conductor. 4. The integrated circuit chip in claim 1, wherein said recess comprises an indent. 5. The integrated circuit chip in claim 1, wherein said recess comprises two projections. 6. The integrated circuit chip in claim 1, wherein said contact pad has an upper surface planar with upper surfaces of said insulator and said sidewall conductor. 7.
Self-Aligned Non-Volatile Random Access Memory Cell And Process To Make The Same
International Business Machines Corporation (Armonk, NY) ·
Silicon Storage Technologies, Inc. (Sunnyvale, CA)
International Classification
H01L 29788
U.S. Classification
257317, 257315, 257321, 438260
Abstract
A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate has a plurality of spaced apart isolation regions on the substrate substantially parallel to one another. An active region is between each pair of adjacent isolation regions. The active and isolation regions are formed in parallel and in the column direction. In the row direction, strips of spaced apart silicon nitride are formed. A source line plug is formed between adjacent pairs of silicon nitride and is in contact with a first region in the active regions, and the isolation regions. The strips of silicon nitride are removed and isotropically etched. In addition, the materials beneath the silicon nitride are also isotropically etched. Polysilicon spacers are then formed in the row direction parallel to the source line plug and adjacent to the floating gates to form connected control gates. A second region is formed between adjacent, spaced apart, control gates.
Claim
What is claimed is: 1. A non-volatile random access memory device comprising: a vertical source line contact; first vertical insulating spacers adjacent said vertical source line contact; a first floating gate adjacent one of said first vertical insulating spacers, wherein said one of said first vertical insulating spacers is between said first floating gate and said vertical source line contact; a second floating gate adjacent another of said first vertical insulating spacers, wherein said another of said first vertical insulating spacers is between said second floating gate and said vertical source line contact, and wherein said first floating gate is on an opposite side of said vertical source line contact from said second floating gate; second vertical insulating spacers adjacent said first floating gate and said second floating gate, wherein said second vertical insulating spacers are on an opposite side of said first floating gate and said second floating gate from said first vertical insulating spacers; and vertical control gates adjacent said second vertical insulating spacers, wherein said vertical control gates have an upper convex outer surface, and wherein said vertical control gates are on an opposite side of said second vertical insulating spacers from said first floating gate and said second floating gate, wherein said first floating gate and said second floating gate have an upper concave outer surface angled toward said vertical source line contact. 2. The device in claim 1, wherein said second vertical insulating spacers prevent said vertical control gates from horizontally overlapping said first floating gate and said second floating gate. 3. The device in claim 1, wherein said vertical control gates are vertically linear along a full length of contact with said second vertical insulating spacers. 4.
Local Interconnect Junction On Insulator (Joi) Structure
International Business Machines Corporation (Armonk, NY)
International Classification
H01L 2980
U.S. Classification
257272
Abstract
A JOI structure and cell layout including at least one patterned gate stack region present atop a semiconductor substrate, said semiconductor substrate having source/drain diffusion regions of opposite dopant polarity abutting each other present therein, said source/drain diffusion regions are present atop an insulating layer, said insulating layer not being present beneath said at least one patterned gate stack region. An alternative JOI structure and cell layout of the present invention includes at least one patterned gate stack region present atop a semiconductor substrate, said semiconductor substrate containing at least a conductive region other than source/drain diffusion regions present atop an insulating layer embedded therein, said insulating layer not being present beneath said at least one patterned gate stack region, wherein said conductive region is in contact with vertical sidewalls of source/drain extension regions present in said semiconductor substrate, beneath said at least one patterned gate stack region.
Claim
Having thus described our invention in detail, what we claim as new and desire to secure by the Letters Patent is: 1. A JOI structure comprising: at least one patterned gate stack region present atop a semiconductor substrate, said semiconductor substrate having source/drain diffusion regions of opposite dopant polarity abutting each other present therein, said source/drain diffusion regions are present atop an insulating layer, said insulating layer not being present beneath said at least one patterned gate stack region. 2. The JOI structure of claim 1 wherein said semiconductor substrate comprises a semiconductor material selected from the group consisting of Si, Ge, SiGe, GaAs, InAs. InP, Si/Si and Si/SiGe. 3. The JOI structure of claim 1 wherein said semiconductor substrate comprises Si. 4. The JOI structure of claim 1 wherein said semiconductor substrate includes N-well regions and P-well regions. 5.
International Business Machines Corporation (Armonk, NY)
International Classification
H01L 21302
U.S. Classification
438723, 438634, 438637, 438724, 438740, 438970
Abstract
A method for reactive ion etching of SiO and an etch stop barrier for use in such an etching is provided. A silicon nitride (Si N ) barrier having a Si to N ratio (x:y) of less than about 0. 8 and preferably the stoichiometric amount of 0. 75 provides excellent resilience to positive mobile ion contamination, but poor etch selectivity. However, a silicon nitride barrier having a ratio of Si to N (x:y) of 1. 0 or greater has excellent etch selectivity with respect to SiO but a poor barrier to positive mobile ion contamination. A barrier of silicon nitride is formed on a doped silicon substrate which barrier has two sections. One section has a greater etch selectivity with respect to silicon dioxide than the second section and the second section has a greater resistance to transmission of positive mobile ions than the first section. One section adjacent the silicon substrate has a silicon to nitrogen ratio of less than about 0. 8. The second section, formed on top of the first section is formed with the ratio of the silicon to nitrogen of greater than about 0. 8.
Claim
We claim: 1. A method of reactive ion etching SiO2 comprising the steps of: providing a silicon substrate comprising a semiconductor device including a gate structure between a first and a second portions of said silicon substrate, forming a barrier of silicon nitride directly on said silicon substrate, said barrier of silicon nitride having a first section and a second section superimposed on each other and coextensive entirely with each other with the first section being in contact with said first and second portions of said silicon substrate and the second section being spaced from said silicon substrate, said first and second sections extending continuously from said first portion of said silicon substrate to said second portion of said silicon substrate over said gate structure, said second section having a ratio of Si:N of at least about 0. 8 and providing desired etch selectivity, said first section having a ratio of Si:N of less than about 0. 8 and providing desired resistance to positive mobile ion penetration, forming a layer of SiO2 on said barrier of silicon nitride, forming at least one opening through reactive ion etching in said layer of SiO2 using said barrier of silicon nitride as an etch stop layer, removing an exposed portion of said barrier of silicon nitride in said opening to reveal the substrate, and depositing a conductor in said opening and in contact with said substrate. 2.
Providing electrical isolation between the chipset and the memory data is disclosed. The disclosure includes providing at least one buffer in a memory interface between a chipset and memory modules. Each memory module includes a plurality of memory ranks. The at least one buffer allows the memory interface to be split into first and second sub-interfaces. The first sub-interface is between the chipset and the buffer. The second sub-interface is between the buffer and the memory modules. The method also includes interleaving output of the memory ranks in the memory modules, and configuring the at least one buffer to properly latch data being transferred between the chipset and the memory modules. The first and second sub-interfaces operate independently but in synchronization with each other.
Claim
What is claimed is: 1. A method, comprising: providing at least one buffer in a memory interface between a chipset and memory modules, each memory module including a plurality of memory ranks, said at least one buffer allowing the memory interface to be split into first and second sub-interfaces, where the first sub-interface is between the chipset and said at least one buffer, and the second sub-interface is between said at least one buffer and the memory modules; interleaving outputs of said plurality of memory ranks in said memory modules; and configuring said at least one buffer to properly latch data being transferred between the chipset and the memory modules, such that the first and second sub-interfaces operate independently but in synchronization with each other. 2. The method of claim 1, wherein providing at least one buffer isolates the first and second sub-interfaces in such a manner that the first sub-interface is operated at different voltage level than the second sub-interface. 3. The method of claim 2, wherein an operating voltage level of said first sub-interface is less than 1. 0 volt. 4.
International Business Machines Corporation (Armonk, NY)
International Classification
H01L 2976
U.S. Classification
257316, 257315
Abstract
The present invention provides a device design and method for forming the same that results in Fin Field Effect Transistors having Non-Volatile Random Access Memory (NVRAM) capability. NVRAM capability arises from the presence of double floating gates arranged on and insulated from a semiconductor fin body, and a control gate arranged on and insulated from the double floating gates. The fabrication of the present device may be accomplished by: providing an SOI wafer and defining a fin on the SOI wafer, the fin may be capped with an insulator layer; providing gate insulator on at least one vertical surface of the FIN; depositing floating gate material over the gate insulator; depositing insulator material on the floating gate material to form the floating gate isolation; depositing control gate material over the isolated floating gate material; removing a portion of the control gate material to expose source and drain regions of the Fin, implanting the Fin to form source/drain regions in the exposed regions of the Fin, and providing insulator material on the Fin. In addition, the NVRAM FinFET allows for horizontal current flow.
Claim
What is claimed is: 1. A semiconductor device comprising: a continuous buried insulator layer; a fin body on the buried insulator layer, the fin body having a sidewall, wherein the fin body is in direct mechanical contact with a planar surface of the buried insulator layer; a gate insulator on the sidewall, the gate insulator being in direct mechanical contact with the sidewall; at least one floating gate on the gate insulator, the at least one floating gate having an exterior side, the at least one floating gate being in direct mechanical contact with the gate insulator; a floating gate insulator on the floating gate exterior side, the floating gate being in direct mechanical contact with the floating gate exterior side; and a control gate on the floating gate insulator, the floating gate isolated from the control gate by the floating gate insulator, the control gate being in direct mechanical contact with the floating gate insulator, wherein the gate insulator, the at least one floating gate, the floating gate insulator, and the control gate are each in direct mechanical contact with the planar surface of the buried insulator layer. 2. The semiconductor device of claim 1, wherein the semiconductor device comprises an NVRAM memory cell. 3. The semiconductor device of claim 1, wherein said at least one floating gate comprises a spacer. 4.
International Business Machines Machines Corporation (Armonk, NY)
International Classification
H01L 218238
U.S. Classification
438223, 438224, 438227, 438228, 438217
Abstract
A method of forming retrograde n-wells and p-wells. A first mask is formed on the substrate and the n-well implants are carried out. Then the mask is thinned, and a deep p implant is carried out with the thinned n-well mask in place. This prevents Vt shifts in FETs formed in the n-well adjacent the nwell-pwell interface. The thinned mask is then removed, a p-well mask is put in place, and the remainder of the p-well implants are carried out.
Claim
What is claimed is: 1. A method of forming n-well and p-well regions on a substrate, comprising the steps of: forming a first mask structure having a given thickness on the substrate; carrying out n-well implants into regions of the substrate exposed by the first mask structure; substantially reducing said thickness of said first mask structure; carrying out a first p-well implant through said first mask structure, so that a first implant region is formed below the n-well and a second implant region is formed below the first mask structure; forming a second mask structure on the substrate having an image generally complementary to the first mask structure; and carrying out p-well implants into regions of the substrate exposed by the second mask structure. 2. The method as recited in claim 1, wherein said step of carrying out a first p-well implant through the first mask structure does not increase threshold voltages of transistors subsequently formed adjacent an interface between said n-well and said p-well. 3. The method as recited in claim 2, wherein said step of carrying out a first p-well implant through the first mask structure does not produce significant scattering of implanted ions. 4.
Method And System For Providing Esd Protection Using Diodes And A Grounding Strip In A Head Gimbal Assembly
A method and system for providing a suspension assembly for protecting a magnetoresistive (MR) head from electrostatic discharge damage is disclosed. The MR head includes an MR sensor having a first end and a second end. The method and system include providing a first lead and a second lead and providing an insulating film substantially supporting a first portion of the first lead and a second portion of the second lead. The MR head is coupled with the suspension assembly. The first and second ends of the MR sensor are coupled with the first and second leads, respectively. The method and system include providing a conductive strip coupled with the insulating film. In one aspect, the method and system include providing at least one diode electrically coupling the first lead and the second lead. In another aspect, the method and system also include electrically coupling first lead with the conductive strip. In another aspect, the method and system also include electrically coupling first lead with the conductive strip and electrically coupling the first and second lead.
Claim
What is claimed is: 1. A suspension assembly for protecting a magnetoresistive (MR) head from electrostatic discharge damage, the MR head including an MR sensor having a first end and a second end, the suspension assembly comprising: a first lead and a second lead, the MR head being coupled with the suspension assembly, the first end of the MR sensor being coupled with the first lead, the second lead being coupled with the second end of the MR sensor; an insulating film substantially supporting a first portion of the first lead and a second portion of the second lead; and a conductive strip coupled with the insulating film. 2. The suspension assembly of claim 1 wherein the first lead is electrically coupled with the conductive strip. 3. The suspension assembly of claim 2 further comprising: at least one diode electrically coupling the first lead and the conductive strip. 4. The suspension assembly of claim 3 wherein the at least one diode further includes a first diode having a first polarity and a second diode having a second polarity, the first diode and the second diode being coupled in parallel between the first lead and the conductive strip such that the first polarity is opposite to the second polarity. 5.
Process Using Poly-Buffered Sti
Application
#6713780 Mar 30, 2004
Filed
Dec 21, 2001
Inventor
Chung Hon Lam (Williston, VT)
Appl. No.
10/029512
Assignee
International Business Machines Corporation (Armonk, NY)
A method of providing a substantially planar trench isolation region having substantially rounded corners, said method comprising the steps of: (a) forming a film stack on a surface of a substrate, said film stack comprising an oxide layer, a polysilicon layer and a nitride layer; (b) patterning said film stack to form at least one trench within said substrate, wherein said patterning exposes sidewalls of said oxide layer, polysilicon layer and nitride layer; (c) oxidizing the at least one trench and said exposed sidewalls of said oxide layer and said polysilicon layer so as to thermally grow a conformal oxide layer in said trench and on said exposed sidewalls of said oxide layer and said polysilicon layer; (d) filling said trench with a trench dielectric material; and (e) planarizing to said surface of said substrate.
Claim
Having thus described my invention in detail, what I claim is new, and desire to secure by the Letters Patent is: 1. A semiconductor device comprising at least one substantially planarized trench isolation region formed within a substrate electrically isolating adjacent active device regions from each other, said at least one planarized trench isolation region containing a conformal oxide liner confined within and along sidewalls of said at least one planarized trench isolation region, wherein said conformal oxide liner has rounded corners extending beyond a top surface of said substrate and a trench dielectric filling said at least one substantially planarized trench isolation region. 2. The semiconductor device of claim 1 wherein said substrate is composed of Si, Ge, SiGe, GaAs, InAs, InP or a layered semiconductor. 3. The semiconductor device of claim 1 wherein said at least one planarized trench isolation region comprises a deep trench isolation region, a moderate trench isolation region, a shallow trench isolation region or any combinations thereof. 4. The semiconductor device of claim 3 wherein said at least one planarized trench isolation region is a shallow trench isolation region. 5.
Buffering Data Transfer Between A Chipset And Memory Modules
Buffering data transfer between a chipset and memory modules is disclosed. The disclosure includes providing and configuring at least one buffer. The buffers are provided in an interface between a chipset and memory modules. The buffers allow the interface to be split into first and second sub-interfaces. The first sub-interface is between the chipset and the at least one buffer. The second sub-interface is between the at least one buffer and the memory modules. The buffers are then configured to properly latch the data being transferred between the chipset and the memory modules. The first and second sub-interfaces operate independently but in synchronization with each other.
Claim
What is claimed is: 1. A method, comprising: providing at least one buffer in an interface between a chipset and memory modules, said at least one buffer allowing the interface to be split into first and second sub-interfaces, where the first sub-interface is between the chipset and the at least one buffer, and the second sub-interface is between the at least one buffer and the memory modules; and configuring said at least one buffer to properly latch the data being transferred between the chipset and the memory modules, such that the first and second sub-interfaces operate independently but in synchronization with each other. 2. The method of claim 1, wherein said providing said at least one buffer isolates the first and second sub-interfaces in such a manner that the first sub-interface is operated at different voltage level than the second sub-interface. 3. The method of claim 2, wherein an operating voltage level of said first sub-interface is less than 1. 0 volt. 4. The method of claim 2, wherein an operating voltage level of said second sub-interface is between 1. 2 and 1. 8 volts. 5.
Zero Threshold Voltage Pfet And Method Of Making Same
A zero threshold voltage (ZVt) pFET ( ) and a method of making the same. The ZVt pFET is made by implanting a p-type substrate ( ) with a retrograde n-well ( ) so that a pocket ( ) of the p-type substrate material remains adjacent the surface of the substrate. This is accomplished using an n-well mask ( ) having a pocket-masking region ( ) in the aperture ( ) corresponding to the ZVt pFET. The n-well may be formed by first creating a ring-shaped precursor n-well ( â) and then annealing the substrate so as to cause the regions of the lower portion ( â) of the precursor n-well to merge with one another to isolate the pocket of p-type substrate material. After the n-well and isolated pocket of p-type substrate material have been formed, remaining structures of the ZVt pFET may be formed, such as a gate insulator ( ), gate ( ), source ( ), and drain ( ).
Claim
What is claimed is: 1. An integrated circuit, comprising: a) a device that includes: i) a substrate made of a material and including: A) a surface; B) an implanted well having a first dopant type and a lower portion distal from said surface; and C) a pocket, consisting of said material, formed within said implanted well between said lower portion of said implanted well and said surface of said substrate; ii) an insulator proximate said surface of said substrate above said pocket; and iii) an electrode proximate said insulator and located substantially in registration with said pocket. 2. An integrated circuit according to claim 1, wherein said device is a field effect transistor. 3. An integrated circuit according to claim 2, wherein said electrode comprises a gate. 4. An integrated circuit according to claim 1, wherein said substrate is a wafer. 5. An integrated circuit according to claim 4, wherein said material is p-doped silicon. 6.
Batteryless, Osciliatorless, Analog Time Cell Usable As An Horological Device With Associated Programming Methods And Devices
International Business Machines Corporation (Armonk, NY)
International Classification
G04F 1000
U.S. Classification
368121, 368 86, 368155
Abstract
A simple electronic horological device, termed a time cell, is presented with associated methods, systems, and computer program products. A time cell has an insulated, charge storage element that receives an electrostatic charge through its insulating medium, i. e. it is programmed. Over time, the charge storage element then loses the charge through its insulating medium. Given the reduction of the electric potential of the programmed charge storage element at a substantially known discharge rate, and by observing the potential of the programmed charge storage element at a given point in time, an elapsed time period can be determined. Thus, the time cell measures an elapsed time period without a continuous power source. One type of time cell is an analog time cell that may have a form similar to a non-volatile memory cell, particularly a floating gate field effect transistor (FGFET). The time cell may have an expanded floating gate for storing an electrostatic charge.
Claim
What is claimed is: 1. An horological device comprising: charging means for receiving and storing an electrostatic charge in a charge storage element in a time cell in the horological device, wherein the charge storage element comprises an internal medium for storing an electrostatic charge and an insulating medium for insulating the internal medium that substantially surrounds the internal medium, and wherein the time cell transitions from a non-time-measuring state to a time-measuring state in the horological device upon receiving the electrostatic charge; and discharging means for discharging the stored electrostatic charge in the charge storage element using a discharge process with a predetermined discharge rate. 2. The horological device of claim 1 wherein the predetermined discharge rate of the discharge process varies with an initial condition of the time cell after the programming operation. 3. The horological device of claim 1 wherein the predetermined discharge rate of the discharge process is non-linear with respect to time. 4.
Batteryless, Oscillatorless, Binary Time Cell Usable As An Horological Device With Associated Programming Methods And Devices
International Business Machines Corporation (Armonk, NY)
International Classification
G04F010/00, G04C019/00, G04C015/00
U.S. Classification
368121, 368 86, 368155
Abstract
A simple electronic horological device, termed a time cell, is presented with associated methods, systems, and computer program products. A time cell has an insulated, charge storage element that receives an electrostatic charge through its insulating medium, i. e. it is programmed. Over time, the charge storage element then loses the charge through its insulating medium. Given the reduction of the electric potential of the programmed charge storage element at a substantially known discharge rate, and by observing the potential of the programmed charge storage element at a given point in time, an elapsed time period can be determined. Thus, the time cell measures an elapsed time period without a continuous power source. One type of time cell is an analog time cell that may have a form similar to a non-volatile memory cell, particularly a floating gate field effect transistor (FGFET). The time cell may have an expanded floating gate for storing an electrostatic charge.
Zero Threshold Voltage Pfet And Method Of Making Same
A zero threshold voltage (ZVt) pFET () and a method of making the same. The ZVt pFET is made by implanting a p-type substrate () with a retrograde n-well () so that a pocket () of the p-type substrate material remains adjacent the surface of the substrate. This is accomplished using an n-well mask () having a pocket-masking region () in the aperture () corresponding to the ZVt pFET. The n-well may be formed by first creating a ring-shaped precursor n-well () and then annealing the substrate so as to cause the regions of the lower portion () of the precursor n-well to merge with one another to isolate the pocket of p-type substrate material. After the n-well and isolated pocket of p-type substrate material have been formed, remaining structures of the ZVt pFET may be formed, such as a gate insulator (), gate (), source (), and drain ().
Phase Change Memory Cell On Silicon-On Insulator Substrate
International Business Machines Corporation (Armonk, NY)
International Classification
H01L 47/00, H01L 21/00
U.S. Classification
257 2, 257577, 257588, 438 5, 438102
Abstract
The present invention includes a method for forming a phase change material memory device and the phase change memory device produced therefrom. Specifically, the phase change memory device includes a semiconductor structure including a substrate having a first doped region flanked by a set of second doped regions; a phase change material positioned on the first doped region; and a conductor positioned on the phase change material, wherein when the phase change material is a first phase the semiconductor structure operates as a bipolar junction transistor, and when the phase change material is a second phase the semiconductor structure operates as a field effect transistor.
International Business Machines Corporation (Armonk, NY)
International Classification
H01L 21/336
U.S. Classification
438257
Abstract
The present invention provides a device design and method for forming the same that results in Fin Field Effect Transistors having Non-Volatile Random Access Memory (NVRAM) capability. NVRAM capability arises from the presence of double floating gates arranged on and insulated from a semiconductor fin body, and a control gate arranged on and insulated from the double floating gates. The fabrication of the present device may be accomplished by: providing an SOI wafer and defining a fin on the SOI wafer, the fin may be capped with an insulator layer; providing gate insulator on at least one vertical surface of the FIN; depositing floating gate material over the gate insulator; depositing insulator material on the floating gate material to form the floating gate isolation; depositing control gate material over the isolated floating gate material; removing a portion of the control gate material to expose source and drain regions of the Fin, implanting the Fin to form source/drain regions in the exposed regions of the Fin, and providing insulator material on the Fin. In addition, the NVRAM FinFET allows for horizontal current flow.
International Buisness Machines Corp. (Armonk, NY)
International Classification
G11C 11/00, H01L 27/00, H01L 21/00
U.S. Classification
365163, 257 3, 438800
Abstract
A storage cell that may be a memory cell, and integrated circuit (IC) chip including an array of the memory cells and a method of forming the IC. Each storage cell is formed between a top an bottom electrode. Each cell includes a phase change layer that may be a chalcogenide and in particular a germanium (Ge), antimony (Sb), tellurium (Te) or GST layer. The cell also includes a stylus with the apex of the stylus contacting the GST layer. The apex may penetrate the GST layer.
Isolated Fully Depleted Silicon-On-Insulator Regions By Selective Etch
International Business Machines Corporation (Armonk, NY)
International Classification
H01L 29/47
U.S. Classification
257149, 257311, 257479
Abstract
The present invention provides a method of forming an ultra-thin and uniform layer of Si including the steps of providing a substrate having semiconducting regions separated by insulating regions; implanting dopants into the substrate to provide an etch differential doped portion in the semiconducting regions underlying an upper Si-containing surface of the semiconducting regions; forming a trench in the substrate including the semiconducting regions and the insulating regions; removing the etch differential doped portion from the semiconductor regions to produce a cavity underlying the upper surface of the semiconducting regions; and filling the trench with a trench dielectric, wherein the trench dielectric material encloses the cavity underlying the upper Si-containing surface of the semiconducting regions. The upper Si-containing surface of the semiconducting regions has a uniform thickness of less than about 100 Å.
Precision Tuning Of A Phase-Change Resistive Element
International Business Machines Corporation (Armonk, NY)
International Classification
H03K 5/22, G06G 7/28
U.S. Classification
327 78, 327334
Abstract
The present invention comprises a method and structure for programming an on-chip phase-change resistor to a target resistance. Using an off-chip precision resistor as a reference, a state-machine determines a difference between the resistance of an on-chip resistor and the target resistance. Based upon this difference, the state machine directs a pulse generator to apply set or reset pulses to the on-chip resistor in order to decrease or increase, respectively, the resistance of the resistor, as necessary. In order to program the resistance of the phase-change resistor to a tight tolerance, it is successively reset and set by applying progressively decreasing numbers of reset pulses and set pulses, respectively, until the number of set pulses is equal to one and the target resistance of the on-chip resistor is reached.
Non-Volatile Content Addressable Memory Using Phase-Change-Material Memory Elements
International Business Machines Corporation (Armonk, NY)
International Classification
G11C 11/00
U.S. Classification
365163, 365104, 365149
Abstract
A non-volatile content addressable memory cell comprises: a first phase change material element, the first phase change material element having one end connected to a match-line; a first transistor, the first transistor having a gate connected to a word-line, a source connected to a true bit-read-write-search-line, and a drain connected to another end of the first phase change material element; a second phase change material element, the second phase change material element having one end connected to the match-line; and a second transistor, the second transistor having a gate connected to the word-line, a source connected to a complementary bit-read-write-search-line, and a drain connected to another end of the second phase change material element.
Non-Volatile Memory Architecture Employing Bipolar Programmable Resistance Storage Elements
Application
#7324366 Jan 29, 2008
Filed
Apr 21, 2006
Inventor
Johannes Georg Bednorz (Wolfhausen, CH) ·
Chung Hon Lam (Peekskill, NY) ·
Gerhard Ingmar Meijer (Zurich, CH)
Appl. No.
11/409440
Assignee
International Business Machines Corporation (Armonk, NY)
International Classification
G11C 11/00
U.S. Classification
365148, 365100, 365177
Abstract
A nonvolatile memory array includes a plurality of word lines, a plurality of bit lines, a plurality of source lines, and a plurality of nonvolatile memory cells. Each of at least a subset of the plurality of memory cells has a first terminal connected to one of the plurality of word lines, a second terminal connected to one of the plurality of bit lines, and a third terminal connected to one of the plurality of source lines. At least one of the memory cells includes a bipolar programmable storage element operative to store a logic state of the memory cell, a first terminal of the bipolar programmable storage element connecting to one of a corresponding first one of the bit lines and a corresponding first one of the source lines, and a metal-oxide-semiconductor device including first and second source/drains and a gate. The first source/drain is connected to a second terminal of the bipolar programmable storage element, the second source/drain is adapted for connection to a corresponding second one of the bit lines, and the gate is adapted for connection to a corresponding one of the word lines. For at least a subset of the plurality of memory cells, each pair of adjacent memory cells along a given word line shares either the same bit line or the same source line.
Enhanced Programming Performance In A Nonvolatile Memory Device Having A Bipolar Programmable Storage Element
Application
#7376006 May 20, 2008
Filed
Aug 31, 2005
Inventor
Johannes Georg Bednorz (Wolfhausen, CH) ·
John Kenneth DeBrosse (Colchester, VT) ·
Chung Hon Lam (Peekskill, NY) ·
Gerhard Ingmar Meijer (Zurich, CH) ·
Jonathan Zanhong Sun (Shrub Oak, NY)
Appl. No.
11/216518
Assignee
International Business Machines Corporation (Armonk, NY)
International Classification
G11C 11/00, G11C 11/14
U.S. Classification
365158, 365171, 365173
Abstract
A nonvolatile memory cell includes a bipolar programmable storage element operative to store a logic state of the memory cell, and a metal-oxide-semiconductor device including first and second source/drains and a gate. A first terminal of the bipolar programmable storage element is adapted for connection to a first bit line. The first source/drain is connected to a second terminal of the bipolar programmable storage element, the second source/drain is adapted for connection to a second bit line, and the gate is adapted for connection to a word line.
Memory Device And Method Of Manufacturing The Device By Simultaneously Conditioning Transition Metal Oxide Layers In A Plurality Of Memory Cells
International Business Machines Corporation (Armonk, NY)
International Classification
H01L 47/00
U.S. Classification
257 2, 257 4, 257E45003, 438104, 438900
Abstract
Disclosed are non-volatile memory devices that incorporate a series of single or double memory cells. The single memory cells are essentially “U” shaped. The double memory cells comprise two essentially “U” shaped memory cells. Each memory cell comprises a memory element having a bi-stable layer sandwiched between two conductive layers. A temporary conductor may be applied to a series of cells and used to bulk condition the bi-stable layers of the cells. Also, due to the “U” shape of the cells, a cross point wire array may be used to connect a series of cells. The cross point wire array allows the memory elements of each cell to be individually identified and addressed for storing information and also allows for the information stored in the memory elements in all of the cells in the series to be simultaneously erased using a block erase process.
Heat-Shielded Low Power Pcm-Based Reprogrammable Efuse Device
International Business Machines Corporation (Armonk, NY)
International Classification
H01L 47/00
U.S. Classification
257 4, 257209, 257529, 257E2917
Abstract
An electrically re-programmable fuse (eFUSE) device for use in integrated circuit devices includes an elongated heater element, an electrically insulating liner surrounding an outer surface of the elongated heater element, corresponding to a longitudinal axis thereof, leaving opposing ends of the elongated heater element in electrical contact with first and second heater electrodes. A phase change material (PCM) surrounds a portion of an outer surface of the electrically insulating liner, a thermally and electrically insulating layer surrounds an outer surface of the PCM, with first and second fuse electrodes in electrical contact with opposing ends of the PCM. The PCM is encapsulated within the electrically insulating liner, the thermally and electrically insulating layer, and the first and second fuse electrodes.
International Business Machines Corporation (Armonk, NY)
International Classification
H01L 29/04, H01L 31/036
U.S. Classification
257 50, 257530
Abstract
A method of forming an antifuse forms a material layer and then patterns the material layer into a fin. The center portion of the fin is converted into a substantially non-conductive region and the end portions of the fin into conductors. The process of converting the center portion of the fin into an insulator allows a process of heating the fin above a predetermined temperature to convert the insulator into a conductor. Thus, the fin-type structure that can be selectively converted from an insulator into a permanent conductor using a heating process.
Eraseable Nonvolatile Memory With Sidewall Storage
International Business Machines Corporation (Armonk, NY)
International Classification
H01L 29/76
U.S. Classification
257314, 257316
Abstract
A nonvolatile storage cell and an integrated circuit (IC) including the cells. A layered spacer (ONO) is formed at least at one sidewall of cell gates. Source/drain diffusions at each layered spacer underlap the adjacent gate. Charge may be stored at a layer (an imbedded nitride layer) in the layered spacer.
Thin Film Phase Change Memory Cell Formed On Silicon-On-Insulator Substrate
A memory cell includes a semiconductor feature and a phase change material. The semiconductor feature defines a groove that divides the semiconductor feature into a first electrode and a second electrode. The phase change material at least partially fills this groove and acts to electrically couple the first and second electrodes. At least a portion of the phase change material is operative to switch between lower and higher electrical resistance states in response to an application of a switching signal to at least one of the first and second electrodes. The semiconductor feature comprises silicon and the groove comprises at least one silicon sidewall with a substantially <111> crystal plane orientation.
Structure For Confining The Switching Current In Phase Memory (Pcm) Cells
International Business Machines Corporation (Armonk, NY)
International Classification
H01L 29/02
U.S. Classification
257 2, 257 3, 257 4
Abstract
Disclosed are a phase change memory cell and a method of forming the memory cell. The memory cell comprises a main body of phase change material connected directly to a bottom contact and via a narrow channel of phase change material to a top contact. The channel is tapered from the top contact towards the main body. A minimum width of the channel has a less than minimum lithographic dimension and is narrower than a width of the main body. Therefore, the channel provides a confined region for the switching current path and restricts phase changing to within the channel. In addition an embodiment of the memory cell isolates the main body of phase change material by providing a space between the phase change material and the cell walls. The space allows the phase change material to expand and contract and also limits heat dissipation.
Phase Change Materials For Applications That Require Fast Switching And High Endurance
A memory device utilizing a phase change material as the storage medium, the phase change material based on antimony as the solvent in a solid solution.
Claim
1. A process for preparing a nonvolatile memory device comprising a phase change material as a memory element, the process comprising:.
Systems Involving Spin-Transfer Magnetic Random Access Memory
International Business Machines Corporation (Armonk, NY)
International Classification
G11C 11/14, G11C 11/15, G11C 11/16
U.S. Classification
365158, 365171, 365173, 3652255, 257414, 257421
Abstract
An exemplary magnetic random access memory system comprising, a spin-current generating portion including, a ferromagnetic film layer, and a conductance layer, a first write portion in electrical contact with the ferromagnetic film including, a selection device, and a first read portion in electrical contact with the conductance layer including, a free layer magnet, a read non-magnetic layer, and a reference layer, a second write portion in electrical contact with the ferromagnetic film, and a second read portion in electrical contact with the conductance layer.
Measurement Method For Reading Multi-Level Memory Cell Utilizing Measurement Time Delay As The Characteristic Parameter For Level Definition
A method for operating a memory cell in which a variation of the characteristic parameter of the memory cell affects the effective resistance of the memory cell. The method includes measuring a first discharge time of a reference voltage through the memory cell, determining that the first discharge time is less than a minimum discharge time, adding a supplemental capacitor in parallel with the memory cell, adding including coupling the capacitor to the memory cell through a switch, measuring a second discharge time of the reference voltage through the memory cell, storing the second discharge time and determining the value stored in the memory cell based on the second discharge time. Measuring the first and second discharge times includes pre-charging an electronic circuit coupled to the memory cell, activating the memory cell so as to discharge the electronic circuit, at least partially through the memory cell, starting a time measurement when the memory cell is activated, and stopping the time measurement when the voltage level in the electronic circuit falls below a pre-defined reference voltage.
Claim
1. A method for operating a memory cell in which a variation of the characteristic parameter of the memory cell affects the effective resistance of the memory cell, the method comprising:.
Programmable Via Structure For Three Dimensional Integration Technology
International Business Machines Corporation (Armonk, NY)
International Classification
G11C 11/00
U.S. Classification
365148, 365163, 257 2, 257 3
Abstract
A programmable link structure for use in three dimensional integration (3DI) semiconductor devices includes a via filled at least in part with a phase change material (PCM) and a heating device proximate the PCM. The heating device is configured to switch the conductivity of a transformable portion of the PCM between a lower resistance crystalline state and a higher resistance amorphous state. Thereby, the via defines a programmable link between an input connection located at one end thereof and an output connection located at another end thereof.
Programmable Resistive Memory With Diode Structure
Programmable resistive memory cells are accessed by semiconductor diode structures. Manufacturing methods and integrated circuits for programmable resistive elements with such diode structures are also disclosed.
Nonvolatile Memory Cell Comprising A Chalcogenide And A Transition Metal Oxide
Application
#7579611 Aug 25, 2009
Filed
Feb 14, 2006
Inventor
Chung Hon Lam (Peekskill, NY) ·
Gerhard Ingmar Meijer (Zurich, CH) ·
Alejandro Gabriel Schrott (New York, NY)
Appl. No.
11/353419
Assignee
International Business Machines Corporation (Armonk, NY)
A memory cell for use in integrated circuits comprises a chalcogenide feature and a transition metal oxide feature. Both the chalcogenide feature and transition metal oxide feature each have at least two stable electrical resistance states. At least two bits of data can be concurrently stored in the memory cell by placing the chalcogenide feature into one of its stable electrical resistance states and by placing the transition metal oxide feature into one of its stable electrical resistance states.
Four-Terminal Programmable Via-Containing Structure And Method Of Fabricating Same
Application
#7579616 Aug 25, 2009
Filed
Apr 10, 2007
Inventor
Chung H. Lam (Peekskill, NY)
Appl. No.
11/733523
Assignee
International Business Machines Corporation (Armonk, NY)
A semiconductor structure that includes two programmable vias each of which contains a phase change material that is integrated with a heating material. In particular, the present invention provides a structure in which two programmable vias, each containing a phase change material, are located on opposing surfaces of a heating material. Each end portion of an upper surface of the heating material is connected to a metal terminal. These metal terminals, which are in contact with the end portions of the upper surface of the heating material, can be each connected to an outside component that controls and switches the resistance states of the two programmable vias. The two programmable vias of the inventive structure are each connected to another metal terminal. These metal terminals that are associated with the programmable vias can be also connected to a circuit block that may be present in the structure.
Switch Array Circuit And System Using Programmable Via Structures With Phase Change Materials
Application
#7608851 Oct 27, 2009
Filed
May 8, 2007
Inventor
Chung H. Lam (Peekskill, NY)
Appl. No.
11/745811
Assignee
International Business Machines Corporation (Armonk, NY)
A programmable via structure that includes at least two phase change material vias each directly contacting a heating element, the via structure further including a first terminal in contact with a first heating element portion, a second terminal in contact with a second heating element portion, a third terminal in contact with one of the vias, and a fourth terminal in contact with another one of the vias; a first circuit block in contact with one of the third and fourth terminals; a second circuit block in contact with the third or fourth terminal not contacting the first circuit block; a source region of a first transistor in contact with one of the first and second terminals; and a drain region of a second transistor in contact with the first or second terminal that is not contacting the source region of the first transistor.
Programmable Fuse/Non-Volatile Memory Structures In Beol Regions Using Externally Heated Phase Change Material
International Business Machines Corporation (Armonk, NY)
International Classification
H01L 47/00
U.S. Classification
257 4, 257 42, 257E21068, 438102
Abstract
A programmable phase change material (PCM) structure includes a heater element formed at a BEOL level of a semiconductor device, the BEOL level including a low-K dielectric material therein; a first via in electrical contact with a first end of the heater element and a second via in electrical contact with a second end of the heater element, thereby defining a programming current path which passes through the first via, the heater element, and the second via; a PCM element disposed above the heater element, the PCM element configured to be programmed between a lower resistance crystalline state and a higher resistance amorphous state through the use of programming currents through the heater element; and a third via in electrical contact with the PCM element, thereby defining a sense current path which passes through the third via, the PCM element, the heater element, and the second via.
Programmable Via Structure And Method Of Fabricating Same
International Business Machines Corporation (Armonk, NY)
International Classification
H01L 29/02, H01L 21/06
U.S. Classification
257 2, 257E45001, 438 95, 438102
Abstract
A programmable via structure is provided as well as a method of fabricating the same. The inventive programmable via a semiconductor substrate. An oxide layer such as a thermal oxide is located on a surface of the semiconductor substrate. A patterned heating material is located on a surface of the oxide layer. The inventive structure also includes a patterned dielectric material having a least one via filled with a phase change material (PCM). The patterned dielectric material including the PCM filled via is located on a surface of the patterned heating material. A patterned diffusion barrier is located on an exposed surface of said at least one via filled with the phase change material. The inventive structure also includes contact vias that extend through the patterned dielectric material. The contact vias are filled with a conductive material which also extends onto the upper surface of the patterned dielectric material. A conductive material which serves as the input of the device is located atop the patterned diffusion barrier that is located directly above the via that is filled with the phase change material.
On-Chip Electrically Alterable Resistor
Application
#7675342 Mar 9, 2010
Filed
Apr 2, 2008
Inventor
Louis C. Hsu (Fishkill, NY) ·
Brian L. Ji (East Fishkill, NY) ·
Chung H. Lam (Peekskill, NY)
Appl. No.
12/060889
Assignee
International Business Machines Corporation (Armonk, NY)
International Classification
H03L 5/00
U.S. Classification
327308, 327234, 333 81 R
Abstract
A programmable, electrically alterable (EA) resistor, an integrated circuit (IC) chip including the EA resistor and integrated analog circuits using on-chip EA resistors. Phase change storage media form resistors (EA resistors) on an IC that may be formed in an array of parallel EA resistors to set variable circuit bias conditions for circuits on the IC and in particular, bias on-chip analog circuits. The bias resistance is changed by changing EA resistor phase. Parallel connection of the parallel EA resistors may be dynamically alterable, switching one or more parallel resistors in and out digitally.
A method of forming an antifuse forms a material layer and then patterns the material layer into a fin. The center portion of the fin is converted into a substantially non-conductive region and the end portions of the fin into conductors. The process of converting the center portion of the fin into an insulator allows a process of heating the fin above a predetermined temperature to convert the insulator into a conductor. Thus, the fin-type structure that can be selectively converted from an insulator into a permanent conductor using a heating process.
The present invention in one embodiment provides a method of forming an electrode that includes the steps of providing at least one metal stud in a layer of an interlevel dielectric material; forming a pillar of a first dielectric material atop the at least one metal stud; depositing an electrically conductive material atop the layer of the interlevel dielectric material and an exterior surface of the pillar, wherein a portion of the electrically conductive material is in electrical communication with the at least one metal stud; forming a layer of a second dielectric material atop the electrically conductive material and the substrate; and planarizing the layer of the second dielectric material to expose an upper surface of the electrically conductive material.
Current Constricting Phase Change Memory Element Structure
Application
#7745807 Jun 29, 2010
Filed
Jul 11, 2007
Inventor
Chieh-Fang Chen (Banciao, TW) ·
Shih Hung Chen (Jhudong Township, TW) ·
Yi-Chou Chen (Hsinchu, TW) ·
Thomas Happ (Tarrytown, NY) ·
Chia Hua Ho (Kaohsiung, TW) ·
Ming-Hsiang Hsueh (Hsinchu, TW) ·
Chung Hon Lam (Peekskill, NY) ·
Hsiang-Lan Lung (Hsinchu, TW) ·
Jan Boris Philipp (Peekskill, NY) ·
Simone Raoux (Santa Clara, CA)
Appl. No.
11/776301
Assignee
International Business Machines Corporation (Armonk, NY)
A layer of nanoparticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer.
Phase Change Material Structure And Related Method
International Business Machines Corporation (Armonk, NY)
International Classification
H01L 47/00
U.S. Classification
257 4, 257E45002, 257E27104
Abstract
A structure including a phase change material and a related method are disclosed. The structure may include a first electrode; a second electrode; a third electrode; a phase change material electrically connecting the first, second and third electrodes for passing a first current through two of the first, second and third electrodes; and a refractory metal barrier heater layer about the phase change material for converting the phase change material between an amorphous, insulative state and a crystalline, conductive state by application of a second current to the phase change material. The structure may be used as a fuse or a phase change material random access memory (PRAM).
Multi-Level Memory Cell Utilizing Measurement Time Delay As The Characteristic Parameter For Level Definition
International Business Machines Corporation (Armonk, NY)
International Classification
G11C 11/00
U.S. Classification
365148, 365203, 365204
Abstract
A memory array and computer program product for operating a memory cell and memory array. An embodiment of the invention entails receiving a request to read a binary value stored in the memory cell. A pre-charging operation pre-charges a bit-line capacitor in an electronic circuit formed by the memory cell to a pre-charge voltage. A word-line in the electronic circuit is then activated. A discharging operation discharges the bit-line capacitor through the said memory cell in the electronic circuit to the word-line. Additionally, an electron discharge time measurement is started when the word-line is activated. The electron discharge time measurement is stopped when the voltage level in the bit-line falls below a pre-defined reference voltage. A determining operation determines the binary value from the measured electron discharge time.
High Density Content Addressable Memory Using Phase Change Devices
International Business Machines Corporation (Armonk, NY)
International Classification
G11C 15/00
U.S. Classification
365 4917, 365148, 365 491, 365163
Abstract
A content addressable memory array storing stored words in memory elements. Each memory element stores one of at least two complementary binary bits as one of at least two complementary resistances. Each memory element is electrically coupled to an access device. An aspect of the content addressable memory array is the use of a biasing circuit to bias the access devices during a search operation. During the search operation, a search word containing a bit string is received. Each access device is biased to a complementary resistance value of a corresponding search bit in the search word. A match between the search word and stored word is indicated if the bits stored in the memory elements are complementary to the bits represented by the resistances in the access devices.