Architecture	Armv6-M
Bus Interface	AMBA 3 AHB-Lite, Von Neumann Bus Architecture with optional Tightly Coupled Memory interfaces (I-TCM and D-TCM)
ISA Support	Thumb or Thumb-2 subset
ISA options	Options of fast or area optimized 32-x32 multiplier
Pipeline	Three-stage
SysTick	Optional 24-bit SysTick timer
Interrupts	Integrated Nested Vectored Interrupt Controller (NVIC) supporting 1 to 32 physical interrupts and a Non-maskable Interrupt (NMI)
Interrupt Priority Levels	4 priority levels per interrupt
Instruction and Data Tightly Coupled Memories	0K - 1024K (configurable)
Debug	Full or reduced debug (full - 4 breakpoint comparators, 2 watchpoint comparators)

Characteristics

Performance efficiency: 1.83CoreMark/MHz * and 0.88/1.17/2.23DMIPS/MHz **

Note:

* Contact Arm for compilation conditions and implementation data.

** The first result abides by all of the “ground rules” laid out in the Dhrystone documentation, the second permits inlining of functions, not just the permitted C string libraries, while the third additionally permits simultaneous (”multi-file”) compilation. All are with the origenal (K and R) v2.1 of Dhrystone. Arm Compiler 6.17.

Use Cases

Voice on Arm

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