URL: http://github.com/Minres/DBT-RISE-RISCV/issues/35
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The AIA spec defines "high half" CSRs for RV32: https://github.com/riscv/riscv-aia/blob/main/src/CSRs.adoc
When enabling AIA we need this CSR interface to exist but accessing existing CSRs.
Eyck said:
we may introduce a feature flag FEAT_AIA (https://github.com/Minres/DBT-RISE-RISCV/blob/main/src/iss/arch/riscv_hart_common.h#L71) to indicate that the upper half of mideleg, mie, and mip should be created.
