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URL: http://github.com/Xilinx/open-nic-shell/issues/68

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FPGA part speed grade on U45N #68

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FPGA part speed grade on U45N#68
@JakaBac

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@JakaBac
JakaBac
opened on Nov 4, 2024

In case of U45N OpenNIC is built for -2LV part. With that part Vivado fails to close timing (WNS -0.993 and TNS -2025.445). I didn't try IDR but I suspect that will also struggle a lot.

I have a SN1022 and I can see that Vccint is 0.85V and not 0.72V. That would imply that the design can be built for -2L part. I haven't tried that yet, but I suspect that it will meet timing even without IDR. From what I know SN1022 and U45N are very closely related.

An owner of an actual U45N also commented on AMD forum that Vccint on his board is 0.85V
AU45N QSFP Port numbering error and part number

But then again I also know somebody who owns a SN1022 and his card has 0.72V Vccint.

Is it possible that first versions of SN1022 had regulators configured for 0.72V and that this was later changed to 0.85V which is still the case on U45N?

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